Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: qcom: sm8150: Add cpufreq HW device node

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Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SM8150 SoCs.

Change-Id: I16e2fb61218383b69fc9867363dbf620c36c3d6a
This commit is contained in:
Shreyas K K
2022-05-20 10:12:07 +05:30
committed by Jeevan Shriram
parent c8276fa9d5
commit eb0e9437ff
1 changed files with 22 additions and 0 deletions
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22
qcom/sm8150.dtsi
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@@ -52,6 +52,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -78,6 +79,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -98,6 +100,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -118,6 +121,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -138,6 +142,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -158,6 +163,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -178,6 +184,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -198,6 +205,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
@@ -884,6 +892,20 @@
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>,
<0x18327800 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,no-accumulative-counter;
#freq-domain-cells = <2>;
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,