mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
ARM: dts: msm: Add SDHC, QUP, RMTFS and MPROC nodes in scuba_auto
Add nodes related to storage, UART, I2C, SPI, RMTFS and MPROC in scuba_auto. Change-Id: Ib2daddcff6216d990e9e4eb4dc622fab7f1ad435
This commit is contained in:
Sanjay
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
935c4fde8d
commit
eda368f1f5
@@ -1 +1,459 @@
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&soc { } ;
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&tlmm {
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/* SDC pin type */
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sdc1_on: sdc1_on {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <16>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <10>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <10>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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sdc1_off: sdc1_off {
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clk {
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pins = "sdc1_clk";
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bias-disable;
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drive-strength = <2>;
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};
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cmd {
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pins = "sdc1_cmd";
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bias-pull-up;
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drive-strength = <2>;
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};
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data {
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pins = "sdc1_data";
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bias-pull-up;
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drive-strength = <2>;
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};
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rclk {
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pins = "sdc1_rclk";
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bias-pull-down;
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};
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};
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_active: qupv3_se0_i2c_active {
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mux {
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pins = "gpio0", "gpio1";
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function = "qup0";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se0_spi_pins: qupv3_se0_spi_pins {
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qupv3_se0_spi_active: qupv3_se0_spi_active {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "qup0";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se0_4uart_pins: qupv3_se0_4uart_pins {
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qupv3_se0_default_ctsrtsrx:
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qupv3_se0_default_ctsrtsrx {
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mux {
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pins = "gpio0", "gpio1", "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1", "gpio3";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se0_default_tx:
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qupv3_se0_default_tx {
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mux {
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pins = "gpio2";
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function = "gpio";
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};
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config {
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pins = "gpio2";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_ctsrx: qupv3_se0_ctsrx {
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mux {
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pins = "gpio0", "gpio3";
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function = "qup0";
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};
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config {
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pins = "gpio0", "gpio3";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se0_rts: qupv3_se0_rts {
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mux {
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pins = "gpio1";
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function = "qup0";
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};
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config {
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pins = "gpio1";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se0_tx: qupv3_se0_tx {
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mux {
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pins = "gpio2";
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function = "qup0";
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};
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config {
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pins = "gpio2";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_active: qupv3_se1_i2c_active {
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mux {
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pins = "gpio4", "gpio5";
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function = "qup1";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio4", "gpio5";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_active: qupv3_se1_spi_active {
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mux {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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function = "qup1";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
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qupv3_se2_i2c_active: qupv3_se2_i2c_active {
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mux {
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pins = "gpio6", "gpio7";
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function = "qup2";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
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mux {
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pins = "gpio6", "gpio7";
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function = "gpio";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se2_spi_pins: qupv3_se2_spi_pins {
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qupv3_se2_spi_active: qupv3_se2_spi_active {
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mux {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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function = "qup2";
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};
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config {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
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mux {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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function = "gpio";
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};
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config {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
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qupv3_se3_default_ctsrtsrx:
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qupv3_se3_default_ctsrtsrx {
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mux {
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pins = "gpio8", "gpio9", "gpio11";
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function = "gpio";
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};
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config {
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pins = "gpio8", "gpio9", "gpio11";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_default_tx:
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qupv3_se3_default_tx {
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mux {
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pins = "gpio10";
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function = "gpio";
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};
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config {
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pins = "gpio10";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_ctsrx: qupv3_se3_ctsrx {
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mux {
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pins = "gpio8", "gpio11";
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function = "qup3";
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};
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config {
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pins = "gpio8", "gpio11";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se3_rts: qupv3_se3_rts {
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mux {
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pins = "gpio9";
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function = "qup3";
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};
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config {
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pins = "gpio9";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_tx: qupv3_se3_tx {
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mux {
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pins = "gpio10";
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function = "qup3";
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};
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config {
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pins = "gpio10";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
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qupv3_se4_2uart_active: qupv3_se4_2uart_active {
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mux {
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pins = "gpio12", "gpio13";
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function = "qup4";
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};
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config {
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pins = "gpio12", "gpio13";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {
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mux {
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pins = "gpio12", "gpio13";
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function = "gpio";
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};
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config {
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pins = "gpio12", "gpio13";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
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qupv3_se5_i2c_active: qupv3_se5_i2c_active {
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mux {
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pins = "gpio14", "gpio15";
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function = "qup5";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
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mux {
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pins = "gpio14", "gpio15";
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function = "gpio";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se5_spi_pins: qupv3_se5_spi_pins {
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qupv3_se5_spi_active: qupv3_se5_spi_active {
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mux {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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function = "qup5";
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};
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config {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
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mux {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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function = "gpio";
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};
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config {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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};
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298
qcom/scuba_auto-qupv3.dtsi
Normal file
298
qcom/scuba_auto-qupv3.dtsi
Normal file
@@ -0,0 +1,298 @@
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&soc {
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@4a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x4a00000 0x60000>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xf6 0x0>;
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qcom,max-num-gpii = <10>;
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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qcom,gpi-ee-offset = <0x10000>;
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dma-coherent;
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status = "ok";
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};
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x4ac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0xe3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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qupv3_se0_i2c: i2c@4a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0x4a80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
|
||||
<&gpi_dma0 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_spi: spi@4a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 1 64 0>,
|
||||
<&gpi_dma0 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* 4-wire UART Instance for DIAG */
|
||||
qupv3_se0_4uart: qcom,qup_uart@4a80000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se0_default_ctsrtsrx>,
|
||||
<&qupv3_se0_default_tx>;
|
||||
pinctrl-1 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>,
|
||||
<&qupv3_se0_tx>;
|
||||
pinctrl-2 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>,
|
||||
<&qupv3_se0_tx>;
|
||||
pinctrl-3 = <&qupv3_se0_default_ctsrtsrx>,
|
||||
<&qupv3_se0_default_tx>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@4a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 3 64 0>,
|
||||
<&gpi_dma0 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@4a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 1 64 0>,
|
||||
<&gpi_dma0 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@4a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 3 64 0>,
|
||||
<&gpi_dma0 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_spi: spi@4a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 1 64 0>,
|
||||
<&gpi_dma0 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x4a8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
|
||||
<&qupv3_se3_default_tx>;
|
||||
pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
|
||||
<&qupv3_se3_tx>;
|
||||
pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
|
||||
<&qupv3_se3_tx>;
|
||||
pinctrl-3 = <&qupv3_se3_default_ctsrtsrx>,
|
||||
<&qupv3_se3_default_tx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Debug UART Instance */
|
||||
qupv3_se4_2uart: qcom,qup_uart@4a90000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x4a90000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_2uart_active>;
|
||||
pinctrl-1 = <&qupv3_se4_2uart_sleep>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@4a94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 3 64 0>,
|
||||
<&gpi_dma0 1 5 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@4a94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 1 64 0>,
|
||||
<&gpi_dma0 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -30,7 +30,10 @@
|
||||
granule = <512>;
|
||||
};
|
||||
|
||||
aliases { };
|
||||
aliases {
|
||||
serial0= &qupv3_se4_2uart ;
|
||||
sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
|
||||
};
|
||||
|
||||
firmware: firmware {};
|
||||
|
||||
@@ -580,6 +583,249 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@00340000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x340000 0x20000>;
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_block 0 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
smem: qcom,smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
qcom,glink {
|
||||
compatible = "qcom,glink";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
glink_modem: modem {
|
||||
qcom,remote-pid = <1>;
|
||||
transport = "smem";
|
||||
mboxes = <&apcs_glb 12>;
|
||||
mbox-names = "mpss_smem";
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "modem";
|
||||
qcom,glink-label = "mpss";
|
||||
|
||||
qcom,modem_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,low-latency;
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
};
|
||||
|
||||
glink_adsp: adsp {
|
||||
qcom,remote-pid = <2>;
|
||||
transport = "smem";
|
||||
mboxes = <&apcs_glb 8>;
|
||||
mbox-names = "adsp_smem";
|
||||
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "adsp";
|
||||
qcom,glink-label = "lpass";
|
||||
|
||||
qcom,adsp_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,low-latency;
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,apr_tal_rpmsg {
|
||||
qcom,glink-channels = "apr_audio_svc";
|
||||
qcom,intents = <0x200 20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,glinkpkt {
|
||||
compatible = "qcom,glinkpkt";
|
||||
|
||||
qcom,glinkpkt-at-mdm0 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DS";
|
||||
qcom,glinkpkt-dev-name = "at_mdm0";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data40-cntl {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
||||
qcom,glinkpkt-dev-name = "smdcntl8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data1 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA1";
|
||||
qcom,glinkpkt-dev-name = "smd7";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data4 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA4";
|
||||
qcom,glinkpkt-dev-name = "smd8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data11 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA11";
|
||||
qcom,glinkpkt-dev-name = "smd11";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-modem {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <435>, <428>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&apcs_glb 14>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <1>;
|
||||
|
||||
modem_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
modem_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
||||
qcom,entry-name = "ipa";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
/* ipa - inbound entry from mss */
|
||||
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
||||
qcom,entry-name = "ipa";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&apcs_glb 10>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
adsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
adsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom-secure-buffer {
|
||||
compatible = "qcom,secure-buffer";
|
||||
};
|
||||
|
||||
qcom_scm: qcomscm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@4744000 {
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
|
||||
reg-names = "hc", "cqhci";
|
||||
|
||||
iommus = <&apps_smmu 0xC0 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
|
||||
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&gcc GCC_SDCC1_AHB_CLK>,
|
||||
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
||||
clock-names = "core", "iface", "ice_core";
|
||||
|
||||
qcom,ice-clk-rates = <300000000 100000000>;
|
||||
|
||||
//interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
|
||||
// <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
|
||||
//interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
//qcom,msm-bus,name = "sdhc1";
|
||||
//qcom,msm-bus,num-cases = <9>;
|
||||
//qcom,msm-bus,num-paths = <2>;
|
||||
//qcom,msm-bus,vectors-KBps =
|
||||
/* No vote */
|
||||
// <0 0>, <0 0>,
|
||||
/* 400 KB/s*/
|
||||
// <1046 1600>,
|
||||
// <1600 1600>,
|
||||
/* 20 MB/s */
|
||||
// <20480 80000>,
|
||||
// <80000 80000>,
|
||||
/* 25 MB/s */
|
||||
// <25600 250000>,
|
||||
// <50000 133320>,
|
||||
/* 50 MB/s */
|
||||
// <51200 250000>,
|
||||
// <65000 133320>,
|
||||
/* 100 MB/s */
|
||||
// <102400 250000>,
|
||||
// <65000 133320>,
|
||||
// /* 200 MB/s */
|
||||
// <204800 800000>,
|
||||
// <200000 300000>,
|
||||
/* 400 MB/s */
|
||||
// <204800 800000>,
|
||||
// <200000 300000>,
|
||||
/* Max. bandwidth */
|
||||
// <1338562 4096000>,
|
||||
// <1338562 4096000>;
|
||||
//qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
||||
// 100750000 200000000 400000000 4294967295>;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
|
||||
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
supports-cqe;
|
||||
|
||||
no-sd;
|
||||
no-sdio;
|
||||
max-frequency = <192000000>;
|
||||
|
||||
//qcom,devfreq,freq-table = <50000000 200000000>;
|
||||
//qcom,scaling-lower-bus-speed-mode = "DDR52";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
qos0 {
|
||||
mask = <0x0f>;
|
||||
vote = <43>;
|
||||
};
|
||||
};
|
||||
|
||||
mccc_debug: syscon@447d200 {
|
||||
compatible = "syscon";
|
||||
reg = <0x447d200 0x100>;
|
||||
@@ -694,6 +940,13 @@
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
|
||||
qcom,rmtfs_sharedmem@0 {
|
||||
compatible = "qcom,sharedmem-uio";
|
||||
reg = <0x0 0x280000>;
|
||||
reg-names = "rmtfs";
|
||||
qcom,client-id = <0x00000001>;
|
||||
qcom,guard-memory;
|
||||
};
|
||||
};
|
||||
|
||||
#include "pm2250-rpm-regulator.dtsi"
|
||||
@@ -768,3 +1021,25 @@
|
||||
};
|
||||
|
||||
#include "msm-arm-smmu-scuba_auto.dtsi"
|
||||
#include "scuba_auto-qupv3.dtsi"
|
||||
|
||||
&sdhc_1 {
|
||||
vdd-supply = <&L20A>;
|
||||
qcom,vdd-voltage-level = <2856000 2856000>;
|
||||
qcom,vdd-current-level = <0 570000>;
|
||||
|
||||
vdd-io-supply = <&L14A>;
|
||||
qcom,vdd-io-always-on;
|
||||
qcom,vdd-io-lpm-sup;
|
||||
qcom,vdd-io-voltage-level = <1800000 1800000>;
|
||||
qcom,vdd-io-current-level = <0 325000>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_on>;
|
||||
pinctrl-1 = <&sdc1_off>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&qupv3_se4_2uart {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user