Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add eMMC & SD card support for sdxpinn

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Add eMMC and SD card support for sdxpinn rumi.

Change-Id: I876cda432380fbd26cea67bd6b9927ea2b554c02
This commit is contained in:
Sachin Gupta
2022-05-20 17:13:31 +05:30
committed by Gerrit - the friendly Code Review server
parent 940828022e
commit f7e9e1afb5
3 changed files with 222 additions and 0 deletions
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102
qcom/sdxpinn-pinctrl.dtsi
View File

@@ -40,6 +40,108 @@
};
};
sdc1_on: sdc1_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_off: sdc1_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc2_on: sdc2_on {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio103";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_off: sdc2_off {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
sd-cd {
pins = "gpio103";
bias-pull-up;
drive-strength = <2>;
};
};
pcie0 {
pcie0_perst_default: pcie0_perst_default {
mux {

44
qcom/sdxpinn-rumi.dtsi
View File

@@ -166,6 +166,50 @@
status = "ok";
};
&sdhc_1 {
status = "ok";
vdd-supply = <&vreg_sdc1_emmc_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L6B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 200000>;
/delete-property/ mmc-ddr-1_8v;
/delete-property/ mmc-hs200-1_8v;
/delete-property/ mmc-hs400-1_8v;
/delete-property/ mmc-hs400-enhanced-strobe;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&vreg_sdc2_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&vreg_sdc2_sd_ls_vccb>;
qcom,vdd-io-voltage-level = <2850000 2850000>;
qcom,vdd-io-current-level = <0 22000>;
is_rumi;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
};
&rpmhcc {
compatible = "fixed-clock";
clock-output-names = "rpmh_clocks";

76
qcom/sdxpinn.dtsi
View File

@@ -22,6 +22,8 @@
aliases {
serial0 = &qupv3_se1_2uart;
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
mmc1 = &sdhc_2; /* SDC2 SD card slot */
};
cpus {
@@ -657,6 +659,80 @@
status = "disabled";
};
sdhc_1: sdhci@8804000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>, <0x08805000 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
non-removable;
supports-cqe;
no-sd;
no-sdio;
qcom,restore-after-cx-collapse;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>;
clock-names = "iface", "core";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000F442C 0x0 0x01
0x090106C0 0x80040868>;
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_EMMC_BCR>;
reset-names = "core_reset";
qos0 {
mask = <0x0f>;
vote = <44>;
};
};
sdhc_2: sdhci@8844000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x08844000 0x1000>;
reg-names = "hc";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
qos0 {
mask = <0x0f>;
vote = <44>;
};
};
tlmm: pinctrl@f000000 {
compatible = "qcom,sdxpinn-pinctrl";
reg = <0x0F000000 0x400000>;