mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
3ea2f68074
Move audio component devicetree to Vendor image and compile as overlay. Change-Id: I1714ad14b602428aec2a9860f54e417da0e99416
713 lines
24 KiB
Plaintext
713 lines
24 KiB
Plaintext
Qualcomm Technologies, Inc. WCD audio CODEC
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WSA macro in Bolero codec
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Required properties:
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- compatible = "qcom,wsa-macro";
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- reg: Specifies the WSA macro base address for Bolero
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soundwire core registers.
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- clock-names : clock names defined for WSA macro
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- clocks : clock handles defined for WSA macro
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- qcom,default-clk-id: Default clk ID used for WSA macro
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- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro
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- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
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required to be configured to receive interrupts
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in BCL block of WSA macro
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WSA slave device as child of Bolero codec
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Required properties:
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- compatible = "qcom,wsa881x";
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- reg: Specifies the WSA slave device base address.
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- qcom,spkr-sd-n-gpio: speaker reset gpio
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Optional properties:
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- bolero-handle: phandle to bolero codec
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Example:
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&bolero {
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wsa_macro: wsa-macro {
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compatible = "qcom,wsa-macro";
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reg = <0x0C2C0000 0x0>;
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clock-names = "wsa_core_clk", "wsa_npl_clk";
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clocks = <&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>;
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qcom,wsa-swr-gpios = &wsa_swr_gpios;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr_0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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wsa881x_1: wsa881x@20170212 {
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compatible = "qcom,wsa881x";
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reg = <0x00 0x20170212>;
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qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
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bolero-handle = <&bolero>;
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};
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};
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};
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};
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VA macro in bolero codec
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Required properties:
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- compatible = "qcom,va-macro";
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- reg: Specifies the VA macro base address for Bolero
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soundwire core registers.
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- clock-names : clock names defined for VA macro
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- clocks : clock handles defined for VA macro
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- qcom,default-clk-id: Default clk ID used for VA macro
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- va-vdd-micb-supply phandle of mic bias supply's regulator device tree node
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- qcom,va-vdd-micb-voltage mic bias supply's voltage level min and max in mV
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- qcom,va-vdd-micb-current mic bias supply's max current in mA
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- qcom,va-dmic-sample-rate Sample rate defined for DMIC connected to VA macro
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Optional properties:
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- qcom,va-clk-mux-select VA macro MCLK MUX selection
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- qcom,va-island-mode-muxsel VA macro island mode MUX selection
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This property is required if qcom,va-clk-mux-select is provided
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- qcom,disable-afe-wakeup-event-listener : If enabled wakeup event listener
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will not be called from VA macro.
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Example:
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&bolero {
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va_macro: va-macro {
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compatible = "qcom,va-macro";
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reg = <0x0C490000 0x0>;
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clock-names = "va_core_clk";
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clocks = <&clock_audio_va 0>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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va-vdd-micb-supply = <&S4A>;
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qcom,va-vdd-micb-voltage = <1800000 1800000>;
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qcom,va-vdd-micb-current = <11200>;
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qcom,va-dmic-sample-rate = <4800000>;
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qcom,va-clk-mux-select = <1>;
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qcom,va-island-mode-muxsel = <0x033A0000>;
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};
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};
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RX macro in bolero codec
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Required properties:
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- compatible = "qcom,rx-macro";
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- reg: Specifies the Rx macro base address for Bolero
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soundwire core registers.
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- clock-names : clock names defined for RX macro
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- clocks : clock handles defined for RX macro
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- qcom,default-clk-id: Default clk ID used for RX macro
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- qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro
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- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
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- qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
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required to be configured to receive interrupts
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in BCL block of WSA macro
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Example:
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&bolero {
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rx_macro: rx-macro {
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compatible = "qcom,rx-macro";
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reg = <0x62EE0000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x62C25020>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr_1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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wcd938x_rx_slave: wcd938x-rx-slave {
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compatible = "qcom,wcd938x-slave";
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};
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};
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};
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};
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TX macro in bolero codec
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Required properties:
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- compatible = "qcom,tx-macro";
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- reg: Specifies the Tx macro base address for Bolero
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soundwire core registers.
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- clock-names : clock names defined for TX macro
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- clocks : clock handles defined for TX macro
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- qcom,tx-swr-gpios: phandle for SWR data and clock GPIOs of TX macro
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- qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro
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Optional properties:
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- compatible = "qcom,swr-mstr";
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- Child of TX macro represent TX SWR master.
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- qcom,swrm-hctl-reg: HW_CTL and CLK_ENABLE bits of SWR module.
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Need Disable HW_CTL bit(to gate HW control)
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for particular Soundwire master version as SW workaround.
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Example:
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&bolero {
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tx_macro: tx-macro {
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compatible = "qcom,tx-macro";
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reg = <0x62EC0000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>
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<&clock_audio_tx_2 0>;
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qcom,tx-swr-gpios = <&tx_swr_gpios>;
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qcom,tx-dmic-sample-rate = <4800000>;
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swr_2: tx_swr_master {
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compatible = "qcom,swr-mstr";
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qcom,swrm-hctl-reg = <0xa53a400>;
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wcd938x_tx_slave: wcd938x-tx-slave {
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compatible = "qcom,wcd938x-slave";
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};
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};
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};
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};
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&bolero {
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rx_macro: rx-macro {
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compatible = "qcom,tx-macro";
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reg = <0x62EC0000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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swr_2: rx_swr_master {
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compatible = "qcom,swr-mstr";
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wcd937x_rx_slave: wcd937x-rx-slave {
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compatible = "qcom,wcd937x-slave";
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};
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};
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};
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};
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WSA macro in LPASS codec
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Required properties:
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- compatible = "qcom,lpass-cdc-wsa-macro";
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- reg: Specifies the WSA macro base address for LPASS codec
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soundwire core registers.
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- clock-names : clock names defined for WSA macro
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- clocks : clock handles defined for WSA macro
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- qcom,default-clk-id: Default clk ID used for WSA macro
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- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro
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- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
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required to be configured to receive interrupts
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in BCL block of WSA macro
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WSA slave device as child of LPASS codec
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Required properties:
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- compatible = "qcom,wsa881x";
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- reg: Specifies the WSA slave device base address.
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- qcom,spkr-sd-n-gpio: speaker reset gpio
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Optional properties:
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- qcom,lpass-cdc-handle: phandle to LPASS codec
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Example:
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&lpass_cdc {
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wsa_macro: wsa-macro {
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compatible = "qcom,lpass-cdc-wsa-macro";
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reg = <0x0C2C0000 0x0>;
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clock-names = "wsa_core_clk", "wsa_npl_clk";
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clocks = <&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>;
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qcom,wsa-swr-gpios = &wsa_swr_gpios;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr_0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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wsa881x_1: wsa881x@20170212 {
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compatible = "qcom,wsa881x";
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reg = <0x00 0x20170212>;
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qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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};
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};
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};
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};
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WSA2 macro in LPASS codec
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Required properties:
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- compatible = "qcom,lpass-cdc-wsa2-macro";
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- reg: Specifies the WSA2 macro base address for LPASS codec
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soundwire core registers.
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- clock-names : clock names defined for WSA2 macro
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- clocks : clock handles defined for WSA2 macro
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- qcom,default-clk-id: Default clk ID used for WSA2 macro
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- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA2 macro
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- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
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required to be configured to receive interrupts
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in BCL block of WSA2 macro
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WSA2 slave device as child of LPASS codec
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Required properties:
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- compatible = "qcom,wsa881x";
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- reg: Specifies the WSA2 slave device base address.
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- qcom,spkr-sd-n-gpio: speaker reset gpio
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Optional properties:
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- qcom,lpass-cdc-handle: phandle to LPASS codec
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Example:
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&lpass_cdc {
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wsa2_macro: wsa2-macro {
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compatible = "qcom,lpass-cdc-wsa2-macro";
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reg = <0x0C2C0000 0x0>;
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qcom,wsa-swr-gpios = <&wsa2_swr_gpios>;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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qcom,thermal-max-state = <11>;
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swr_3: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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wsa881x_1: wsa881x@20170212 {
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compatible = "qcom,wsa881x";
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reg = <0x00 0x20170212>;
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qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
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qcom,lpass-cdc-handle = <&lpass_cdc>;
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};
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};
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};
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};
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VA macro in LPASS codec
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Required properties:
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- compatible = "qcom,lpass-cdc-va-macro";
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- reg: Specifies the VA macro base address for LPASS
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soundwire core registers.
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- clock-names : clock names defined for VA macro
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- clocks : clock handles defined for VA macro
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- qcom,default-clk-id: Default clk ID used for VA macro
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- qcom,va-dmic-sample-rate Sample rate defined for DMIC connected to VA macro
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- qcom,va-swr-gpios: phandle for SWR data and clock GPIOs of VA macro
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Optional properties:
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- compatible = "qcom,swr-mstr";
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- Child of VA macro represent VA SWR master.
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- qcom,va-clk-mux-select VA macro MCLK MUX selection
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- qcom,va-island-mode-muxsel VA macro island mode MUX selection
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This property is required if qcom,va-clk-mux-select is provided
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Example:
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&lpass_cdc {
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va_macro: va-macro {
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compatible = "qcom,lpass-cdc-va-macro";
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reg = <0x0C490000 0x0>;
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clock-names = "va_core_clk";
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clocks = <&clock_audio_va 0>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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va-vdd-micb-supply = <&S4A>;
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qcom,va-vdd-micb-voltage = <1800000 1800000>;
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qcom,va-vdd-micb-current = <11200>;
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qcom,va-dmic-sample-rate = <4800000>;
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qcom,va-clk-mux-select = <1>;
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qcom,va-island-mode-muxsel = <0x033A0000>;
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qcom,is-used-swr-gpio = <1>;
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qcom,va-swr-gpios = <&va_swr_gpios>;
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swr_2: tx_swr_master {
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compatible = "qcom,swr-mstr";
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wcd938x_tx_slave: wcd938x-tx-slave {
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compatible = "qcom,wcd938x-slave";
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};
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};
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};
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};
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RX macro in LPASS codec
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Required properties:
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- compatible = "qcom,lpass-cdc-rx-macro";
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- reg: Specifies the Rx macro base address for LPASS
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soundwire core registers.
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- clock-names : clock names defined for RX macro
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- clocks : clock handles defined for RX macro
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- qcom,default-clk-id: Default clk ID used for RX macro
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- qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro
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- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
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- qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
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required to be configured to receive interrupts
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in BCL block of WSA macro
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Example:
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&lpass_cdc {
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rx_macro: rx-macro {
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compatible = "qcom,lpass-cdc-rx-macro";
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reg = <0x62EE0000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x62C25020>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr_1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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wcd938x_rx_slave: wcd938x-rx-slave {
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compatible = "qcom,wcd938x-slave";
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};
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};
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};
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};
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TX macro in LPASS codec
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Required properties:
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- compatible = "qcom,lpass-cdc-tx-macro";
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- reg: Specifies the Tx macro base address for LPASS
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soundwire core registers.
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- clock-names : clock names defined for TX macro
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- clocks : clock handles defined for TX macro
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- qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro
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Example:
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&lpass_cdc {
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tx_macro: tx-macro {
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compatible = "qcom,lpass-cdc-tx-macro";
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reg = <0x62EC0000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>
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<&clock_audio_tx_2 0>;
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qcom,tx-dmic-sample-rate = <4800000>;
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};
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};
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Tanggu Codec
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Required properties:
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- compatible: "qcom,wcd937x-codec";
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- qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also
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corresponding master port type it need to attach.
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format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>
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same port_id configurations have to be grouped, and in ascending order.
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- qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also
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corresponding master port type it need to attach.
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format: <port_id,slave_port_type, ch_mask, ch_rate, master_port_type>
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same port_id configurations have to be grouped, and in ascending order.
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- qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio
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configuration. If this property is not defined, it is
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expected to atleast define "qcom,cdc-reset-gpio" property.
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- qcom,rx-slave: phandle reference of Soundwire Rx slave device.
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- qcom,tx-slave: phandle reference of Soundwire Tx slave device.
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Optional properties:
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- cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node.
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- qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV.
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- qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA.
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- cdc-vddio-supply: phandle of io supply's regulator device tree node.
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- qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV.
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- qcom,cdc-vddio-current: io supply's max current in mA.
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- cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node.
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- qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV.
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- qcom,cdc-vdd-buck-current: buck supply's max current in mA.
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- cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node.
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- qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV.
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- qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA.
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- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
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hardware probe. Supplies in this list will be
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stay enabled.
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- qcom,cdc-on-demand-supplies: List of supplies which can be enabled
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dynamically.
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Supplies in this list are off by default.
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Example:
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wcd937x_codec: wcd937x-codec {
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compatible = "qcom,wcd937x-codec";
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,
|
|
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
|
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
|
<4 DSD_R 0x2 0 DSD_R>;
|
|
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
|
|
<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
|
|
<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
|
|
<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
|
|
<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
|
|
<3 DMIC5 0x8 0 DMIC7>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
|
|
qcom,rx-slave = <&wcd937x_rx_slave>;
|
|
qcom,tx-slave = <&wcd937x_tx_slave>;
|
|
|
|
cdc-vdd-buck-supply = <&S4A>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <650000>;
|
|
|
|
cdc-vdd-rxtx-supply = <&S4A>;
|
|
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rxtx-current = <30000>;
|
|
|
|
cdc-vddio-supply = <&S4A>;
|
|
qcom,cdc-vddio-voltage = <1800000 1800000>;
|
|
qcom,cdc-vddio-current = <30000>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
|
qcom,cdc-vdd-mic-bias-current = <30000>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
|
"cdc-vddio";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
|
"cdc-vdd-mic-bias";
|
|
};
|
|
|
|
Traverso Codec
|
|
|
|
Required properties:
|
|
- compatible: "qcom,wcd938x-codec";
|
|
- qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also
|
|
corresponding master port type it need to attach.
|
|
format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>
|
|
same port_id configurations have to be grouped, and in ascending order.
|
|
- qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also
|
|
corresponding master port type it need to attach.
|
|
format: <port_id,slave_port_type, ch_mask, ch_rate, master_port_type>
|
|
same port_id configurations have to be grouped, and in ascending order.
|
|
- qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio
|
|
configuration. If this property is not defined, it is
|
|
expected to atleast define "qcom,cdc-reset-gpio" property.
|
|
- qcom,rx-slave: phandle reference of Soundwire Rx slave device.
|
|
- qcom,tx-slave: phandle reference of Soundwire Tx slave device.
|
|
|
|
Optional properties:
|
|
|
|
- cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node.
|
|
- qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV.
|
|
- qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA.
|
|
|
|
- cdc-vddio-supply: phandle of io supply's regulator device tree node.
|
|
- qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV.
|
|
- qcom,cdc-vddio-current: io supply's max current in mA.
|
|
|
|
- cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node.
|
|
- qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV.
|
|
- qcom,cdc-vdd-buck-current: buck supply's max current in mA.
|
|
|
|
- cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node.
|
|
- qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV.
|
|
- qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA.
|
|
|
|
- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
|
|
hardware probe. Supplies in this list will be
|
|
stay enabled.
|
|
|
|
- qcom,cdc-on-demand-supplies: List of supplies which can be enabled
|
|
dynamically.
|
|
Supplies in this list are off by default.
|
|
|
|
Example:
|
|
wcd938x_codec: wcd938x-codec {
|
|
compatible = "qcom,wcd938x-codec";
|
|
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
|
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,
|
|
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
|
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
|
<4 DSD_R 0x2 0 DSD_R>;
|
|
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
|
|
<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
|
|
<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
|
|
<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
|
|
<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
|
|
<3 DMIC5 0x8 0 DMIC7>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
|
|
qcom,rx-slave = <&wcd938x_rx_slave>;
|
|
qcom,tx-slave = <&wcd938x_tx_slave>;
|
|
|
|
cdc-vdd-buck-supply = <&S4A>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <650000>;
|
|
|
|
cdc-vdd-rxtx-supply = <&S4A>;
|
|
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rxtx-current = <30000>;
|
|
|
|
cdc-vddio-supply = <&S4A>;
|
|
qcom,cdc-vddio-voltage = <1800000 1800000>;
|
|
qcom,cdc-vddio-current = <30000>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
|
qcom,cdc-vdd-mic-bias-current = <30000>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
|
"cdc-vddio";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
|
|
"cdc-vdd-mic-bias";
|
|
};
|
|
|
|
Bolero Clock Resource Manager
|
|
|
|
Required Properties:
|
|
- compatible = "qcom,bolero-clk-rsc-mngr";
|
|
- qcom,fs-gen-sequence: Register sequence for fs clock generation
|
|
- clock-names : clock names defined for WSA macro
|
|
- clocks : clock handles defined for WSA macro
|
|
|
|
Optional Properties:
|
|
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
|
|
- qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select
|
|
- qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select
|
|
|
|
Example:
|
|
&bolero {
|
|
bolero-clock-rsc-manager {
|
|
compatible = "qcom,bolero-clk-rsc-mngr";
|
|
qcom,fs-gen-sequence = <0x3000 0x1>,
|
|
<0x3004 0x1>, <0x3080 0x2>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
|
|
qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
|
|
qcom,va_mclk_mode_muxsel = <0x033A0000>;
|
|
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk",
|
|
"rx_npl_clk", "wsa_core_clk", "wsa_npl_clk",
|
|
"va_core_clk", "va_npl_clk";
|
|
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
|
|
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
|
|
<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
|
|
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
|
|
};
|
|
};
|
|
|
|
LPASS Digital Codec Clock Resource Manager
|
|
|
|
Required Properties:
|
|
- compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
|
- qcom,fs-gen-sequence: Register sequence for fs clock generation
|
|
- clock-names : clock names defined for WSA macro
|
|
- clocks : clock handles defined for WSA macro
|
|
|
|
Optional Properties:
|
|
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
|
|
- qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select
|
|
- qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select
|
|
|
|
Example:
|
|
&lpass_cdc {
|
|
lpass-cdc-clk-rsc-mngr {
|
|
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
|
qcom,fs-gen-sequence = <0x3000 0x1>,
|
|
<0x3004 0x1>, <0x3080 0x2>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
|
|
qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
|
|
qcom,va_mclk_mode_muxsel = <0x033A0000>;
|
|
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk",
|
|
"rx_npl_clk", "wsa_core_clk", "wsa_npl_clk",
|
|
"va_core_clk", "va_npl_clk";
|
|
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
|
|
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
|
|
<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
|
|
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
|
|
};
|
|
};
|
|
|
|
WSA Analog Codec
|
|
|
|
Required Properties:
|
|
- compatible = "qcom,wsa881x-i2c-codec";
|
|
- reg: Specifies the I2C chip address.
|
|
- clock-names : clock names defined for WSA master clock
|
|
- clocks : clock handles defined for WSA master clock
|
|
- qcom,wsa-analog-clk-gpio: Specificies WSA_MCLK GPIO handle
|
|
- qcom,wsa-analog-reset-gpio: Specifies WSA reset GPIO handle
|
|
|
|
Optional Properties:
|
|
- qcom,wsa-analog-vi-gpio: Specifies WSA VI sense GPIO handle
|
|
|
|
Example:
|
|
&qupv3_se1_i2c {
|
|
wsa881x_i2c_f: wsa881x-i2c-codec@f {
|
|
compatible = "qcom,wsa881x-i2c-codec";
|
|
reg = <0x0f>;
|
|
clock-names = "wsa_mclk";
|
|
clocks = <&wsa881x_analog_clk 0>;
|
|
qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
|
|
qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
|
|
};
|
|
|
|
wsa881x_i2c_45: wsa881x-i2c-codec@45 {
|
|
compatible = "qcom,wsa881x-i2c-codec";
|
|
reg = <0x045>;
|
|
};
|
|
};
|
|
|
|
WSA883x Soundwire slave device as child of Soundwire master in Bolero codec
|
|
|
|
Required properties:
|
|
- compatible = "qcom,wsa883x";
|
|
- reg: Specifies the WSA883x soundwire slave unique device address
|
|
- qcom,spkr-sd-n-gpio: speaker reset gpio
|
|
|
|
Optional properties:
|
|
- bolero-handle: phandle to bolero codec
|
|
- cdc-vdd-1p8-supply: phandle of VDD 1.8V supply's regulator device tree node.
|
|
- qcom,cdc-vdd-1p8-voltage: VDD 1.8V supply's voltage level min and max in mV.
|
|
- qcom,cdc-vdd-1p8-current: VDD 1.8V supply's max current in mA.
|
|
- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
|
|
hardware probe. Supplies in this list will be
|
|
stay enabled.
|
|
|
|
Example:
|
|
wsa883x_0221: wsa883x@02170221 {
|
|
compatible = "qcom,wsa883x";
|
|
reg = <0x02 0x02170221>;
|
|
qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
|
|
bolero-handle = <&bolero>;
|
|
|
|
cdc-vdd-1p8-supply = <&S10B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <20000>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
};
|
|
|
|
Haptics Soundwire slave device as child of Soundwire master in Bolero codec
|
|
|
|
Required properties:
|
|
- compatible: "qcom,swr-haptics", or "qcom,pm8350b-swr-haptics".
|
|
- reg: Specifies the haptics soundwire slave unique device address.
|
|
- swr-slave-supply: Specify the phandle of the regulator device to take
|
|
haptics soundwire slave out of reset.
|
|
- qcom,rx_swr_ch_map: Specify the mapping of soundwire rx slave port configuration.
|
|
format: <port_id, ch_mask, ch_rate, num_ch, port_type>.
|
|
|
|
Example:
|
|
swr_haptics: swr_haptics@f0170220 {
|
|
compatible = "qcom,pm8350b-swr-haptics";
|
|
reg = <0x01 0xf0170220>;
|
|
swr-slave-supply = <&hap_swr_slave_reg>;
|
|
qcom,rx_swr_ch_map = <0 0x1 0xF 0 PCM_OUT1>;
|
|
};
|
|
|
|
SWR MIC Soundwire slave device as child of Soundwire master in digital codec
|
|
|
|
Required properties:
|
|
- compatible = "qcom,swr-dmic";
|
|
- reg: Specifies the SWR MIC soundwire slave unique device address
|
|
- qcom,swr-dmic-prefix: Prefix to use for alsa widgets and routes
|
|
- qcom,codec-name: Name for the corresponding swr mic codec
|
|
- qcom,swr-dmic-supply: Mic bias widget name that turns on this device's power supply
|
|
- qcom,wcd-handle: pHandle to wcd node that can enable this device's supply
|
|
|
|
Example:
|
|
swr_dmic_01: dmic_swr@58350220 {
|
|
compatible = "qcom,swr-dmic";
|
|
reg = <0x08 0x58350220>;
|
|
qcom,swr-dmic-prefix = "SWR_MIC0";
|
|
qcom,codec-name = "swr-dmic-01";
|
|
qcom,swr-dmic-supply = "MIC BIAS1 Standalone";
|
|
qcom,wcd-handle = <&wcd938x_codec>;
|
|
};
|