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audio: dts: Compile audio component devicetree as overlay

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Move audio component devicetree to Vendor image and compile
as overlay.

Change-Id: I1714ad14b602428aec2a9860f54e417da0e99416
This commit is contained in:
Meng Wang
2021-03-19 15:19:27 +08:00
parent 73d6f57575
commit 3ea2f68074
20 changed files with 7451 additions and 0 deletions
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9
Kbuild Normal file
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dtbo-y += waipio-audio.dtbo \
waipio-audio-cdp.dtbo \
waipio-audio-mtp.dtbo \
waipio-audio-qrd.dtbo
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

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AUDIO_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M)
AUDIO_KERNEL_ROOT=$(AUDIO_DEVICETREE_ROOT)/../../opensource/audio-kernel/include
KBUILD_OPTIONS += KBUILD_DTC_INCLUDE=$(AUDIO_KERNEL_ROOT)
KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=.
KBUILD_OPTIONS += KERNEL_ROOT=$(ROOT_DIR)/$(KERNEL_DIR)
KBUILD_OPTIONS += MODNAME=audio-devicetree
all: dtbs
dtbs:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules dtbs $(KBUILD_OPTIONS)
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

202
bindings/qcom,lpi-pinctrl.txt Normal file
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Qualcomm Technologies, Inc. LPI GPIO controller driver
This DT bindings describes the GPIO controller driver
being added for supporting LPI (Low Power Island) TLMM
from QTI chipsets.
Following properties are for LPI GPIO controller device main node.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,lpi-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base of the GPIO controller and length.
- qcom,num-gpios:
Usage: required
Value type: <u32>
Definition: Number of GPIOs supported by the controller.
- qcom,lpi-offset-tbl
Usage: required
Value type: <u32-array>
Definition: Offset table of GPIOs supported by the controller.
- gpio-controller:
Usage: required
Value type: <none>
Definition: Used to mark the device node as a GPIO controller.
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: Must be 2;
The first cell will be used to define gpio number and the
second denotes the flags for this gpio.
- #qcom,slew-reg:
Usage: optional
Value type: <prop-encoded-array>
Definition: Register base of the slew register and length.
- #qcom,lpi-slew-offset-tbl:
Usage: optional
Value type: <u32-array>
Definition: Offset table that points to each pin's shift value
position in bits in the slew register base for slew
settings.
- #qcom,lpi-slew-base-tbl:
Usage: optional
Value type: <u32-array>
Definition: Table points to physical address for corresponding
slew registers.
Please refer to ../gpio/gpio.txt for general description of GPIO bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin or a list of pins. This configuration can include the
mux function to select on those pin(s), and various pin configuration
parameters, as listed below.
SUBNODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are: gpio0-gpio31 for LPI.
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
"gpio",
"func1",
"func2",
"func3",
"func4",
"func5"
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-bus-hold:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as bus-keeper mode.
- bias-pull-up:
Usage: optional
Value type: <empty>
Definition: The specified pins should be configured as pull up.
- input-enable:
Usage: optional
Value type: <none>
Definition: The specified pins are put in input mode.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
- qcom,drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins.
- slew-rate:
Usage: optional
Value type: <u32>
Definition: Selects the slew rate for the specified pins.
Example:
lpi_tlmm: lpi_pinctrl@152c000 {
compatible = "qcom,lpi-pinctrl";
qcom,num-gpios = <32>;
reg = <0x152c000 0>;
qcom,slew-reg = <0x355a000 0x0>;
gpio-controller;
#gpio-cells = <2>;
qcom,lpi-offset-tbl = <0x00000010>, <0x00000020>,
<0x00000030>, <0x00000040>,
<0x00000050>, <0x00000060>,
<0x00000070>, <0x00000080>,
<0x00000090>, <0x00000100>,
<0x00000110>, <0x00000120>,
<0x00000130>, <0x00000140>,
<0x00000150>, <0x00000160>,
<0x00000170>, <0x00000180>,
<0x00000190>, <0x00000200>,
<0x00000210>;
qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
<0x00000004>, <0x00000008>,
<0x0000000A>, <0x0000000C>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000010>, <0x00000012>,
<0x00000000>, <0x00000000>;
hph_comp_active: hph_comp_active {
mux {
pins = "gpio22";
function = "func1";
};
config {
pins = "gpio22";
output-high;
qcom,drive-strength = <8>;
};
};
hph_comp_sleep: hph_comp_sleep {
mux {
pins = "gpio22";
function = "func1";
};
config {
pins = "gpio22";
qcom,drive-strength = <2>;
slew-rate = <1>;
};
};
};

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Qualcomm Technologies, Inc. WCD audio CODEC
WSA macro in Bolero codec
Required properties:
- compatible = "qcom,wsa-macro";
- reg: Specifies the WSA macro base address for Bolero
soundwire core registers.
- clock-names : clock names defined for WSA macro
- clocks : clock handles defined for WSA macro
- qcom,default-clk-id: Default clk ID used for WSA macro
- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro
- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
required to be configured to receive interrupts
in BCL block of WSA macro
WSA slave device as child of Bolero codec
Required properties:
- compatible = "qcom,wsa881x";
- reg: Specifies the WSA slave device base address.
- qcom,spkr-sd-n-gpio: speaker reset gpio
Optional properties:
- bolero-handle: phandle to bolero codec
Example:
&bolero {
wsa_macro: wsa-macro {
compatible = "qcom,wsa-macro";
reg = <0x0C2C0000 0x0>;
clock-names = "wsa_core_clk", "wsa_npl_clk";
clocks = <&clock_audio_wsa_1 0>,
<&clock_audio_wsa_2 0>;
qcom,wsa-swr-gpios = &wsa_swr_gpios;
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr_0: wsa_swr_master {
compatible = "qcom,swr-mstr";
wsa881x_1: wsa881x@20170212 {
compatible = "qcom,wsa881x";
reg = <0x00 0x20170212>;
qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
bolero-handle = <&bolero>;
};
};
};
};
VA macro in bolero codec
Required properties:
- compatible = "qcom,va-macro";
- reg: Specifies the VA macro base address for Bolero
soundwire core registers.
- clock-names : clock names defined for VA macro
- clocks : clock handles defined for VA macro
- qcom,default-clk-id: Default clk ID used for VA macro
- va-vdd-micb-supply phandle of mic bias supply's regulator device tree node
- qcom,va-vdd-micb-voltage mic bias supply's voltage level min and max in mV
- qcom,va-vdd-micb-current mic bias supply's max current in mA
- qcom,va-dmic-sample-rate Sample rate defined for DMIC connected to VA macro
Optional properties:
- qcom,va-clk-mux-select VA macro MCLK MUX selection
- qcom,va-island-mode-muxsel VA macro island mode MUX selection
This property is required if qcom,va-clk-mux-select is provided
- qcom,disable-afe-wakeup-event-listener : If enabled wakeup event listener
will not be called from VA macro.
Example:
&bolero {
va_macro: va-macro {
compatible = "qcom,va-macro";
reg = <0x0C490000 0x0>;
clock-names = "va_core_clk";
clocks = <&clock_audio_va 0>;
qcom,default-clk-id = <TX_CORE_CLK>;
va-vdd-micb-supply = <&S4A>;
qcom,va-vdd-micb-voltage = <1800000 1800000>;
qcom,va-vdd-micb-current = <11200>;
qcom,va-dmic-sample-rate = <4800000>;
qcom,va-clk-mux-select = <1>;
qcom,va-island-mode-muxsel = <0x033A0000>;
};
};
RX macro in bolero codec
Required properties:
- compatible = "qcom,rx-macro";
- reg: Specifies the Rx macro base address for Bolero
soundwire core registers.
- clock-names : clock names defined for RX macro
- clocks : clock handles defined for RX macro
- qcom,default-clk-id: Default clk ID used for RX macro
- qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
- qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
required to be configured to receive interrupts
in BCL block of WSA macro
Example:
&bolero {
rx_macro: rx-macro {
compatible = "qcom,rx-macro";
reg = <0x62EE0000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>,
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x62C25020>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr_1: rx_swr_master {
compatible = "qcom,swr-mstr";
wcd938x_rx_slave: wcd938x-rx-slave {
compatible = "qcom,wcd938x-slave";
};
};
};
};
TX macro in bolero codec
Required properties:
- compatible = "qcom,tx-macro";
- reg: Specifies the Tx macro base address for Bolero
soundwire core registers.
- clock-names : clock names defined for TX macro
- clocks : clock handles defined for TX macro
- qcom,tx-swr-gpios: phandle for SWR data and clock GPIOs of TX macro
- qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro
Optional properties:
- compatible = "qcom,swr-mstr";
- Child of TX macro represent TX SWR master.
- qcom,swrm-hctl-reg: HW_CTL and CLK_ENABLE bits of SWR module.
Need Disable HW_CTL bit(to gate HW control)
for particular Soundwire master version as SW workaround.
Example:
&bolero {
tx_macro: tx-macro {
compatible = "qcom,tx-macro";
reg = <0x62EC0000 0x0>;
clock-names = "tx_core_clk", "tx_npl_clk";
clocks = <&clock_audio_tx_1 0>
<&clock_audio_tx_2 0>;
qcom,tx-swr-gpios = <&tx_swr_gpios>;
qcom,tx-dmic-sample-rate = <4800000>;
swr_2: tx_swr_master {
compatible = "qcom,swr-mstr";
qcom,swrm-hctl-reg = <0xa53a400>;
wcd938x_tx_slave: wcd938x-tx-slave {
compatible = "qcom,wcd938x-slave";
};
};
};
};
&bolero {
rx_macro: rx-macro {
compatible = "qcom,tx-macro";
reg = <0x62EC0000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
swr_2: rx_swr_master {
compatible = "qcom,swr-mstr";
wcd937x_rx_slave: wcd937x-rx-slave {
compatible = "qcom,wcd937x-slave";
};
};
};
};
WSA macro in LPASS codec
Required properties:
- compatible = "qcom,lpass-cdc-wsa-macro";
- reg: Specifies the WSA macro base address for LPASS codec
soundwire core registers.
- clock-names : clock names defined for WSA macro
- clocks : clock handles defined for WSA macro
- qcom,default-clk-id: Default clk ID used for WSA macro
- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro
- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
required to be configured to receive interrupts
in BCL block of WSA macro
WSA slave device as child of LPASS codec
Required properties:
- compatible = "qcom,wsa881x";
- reg: Specifies the WSA slave device base address.
- qcom,spkr-sd-n-gpio: speaker reset gpio
Optional properties:
- qcom,lpass-cdc-handle: phandle to LPASS codec
Example:
&lpass_cdc {
wsa_macro: wsa-macro {
compatible = "qcom,lpass-cdc-wsa-macro";
reg = <0x0C2C0000 0x0>;
clock-names = "wsa_core_clk", "wsa_npl_clk";
clocks = <&clock_audio_wsa_1 0>,
<&clock_audio_wsa_2 0>;
qcom,wsa-swr-gpios = &wsa_swr_gpios;
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr_0: wsa_swr_master {
compatible = "qcom,swr-mstr";
wsa881x_1: wsa881x@20170212 {
compatible = "qcom,wsa881x";
reg = <0x00 0x20170212>;
qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
};
};
};
};
WSA2 macro in LPASS codec
Required properties:
- compatible = "qcom,lpass-cdc-wsa2-macro";
- reg: Specifies the WSA2 macro base address for LPASS codec
soundwire core registers.
- clock-names : clock names defined for WSA2 macro
- clocks : clock handles defined for WSA2 macro
- qcom,default-clk-id: Default clk ID used for WSA2 macro
- qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA2 macro
- qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
required to be configured to receive interrupts
in BCL block of WSA2 macro
WSA2 slave device as child of LPASS codec
Required properties:
- compatible = "qcom,wsa881x";
- reg: Specifies the WSA2 slave device base address.
- qcom,spkr-sd-n-gpio: speaker reset gpio
Optional properties:
- qcom,lpass-cdc-handle: phandle to LPASS codec
Example:
&lpass_cdc {
wsa2_macro: wsa2-macro {
compatible = "qcom,lpass-cdc-wsa2-macro";
reg = <0x0C2C0000 0x0>;
qcom,wsa-swr-gpios = <&wsa2_swr_gpios>;
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,thermal-max-state = <11>;
swr_3: wsa_swr_master {
compatible = "qcom,swr-mstr";
wsa881x_1: wsa881x@20170212 {
compatible = "qcom,wsa881x";
reg = <0x00 0x20170212>;
qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
};
};
};
};
VA macro in LPASS codec
Required properties:
- compatible = "qcom,lpass-cdc-va-macro";
- reg: Specifies the VA macro base address for LPASS
soundwire core registers.
- clock-names : clock names defined for VA macro
- clocks : clock handles defined for VA macro
- qcom,default-clk-id: Default clk ID used for VA macro
- qcom,va-dmic-sample-rate Sample rate defined for DMIC connected to VA macro
- qcom,va-swr-gpios: phandle for SWR data and clock GPIOs of VA macro
Optional properties:
- compatible = "qcom,swr-mstr";
- Child of VA macro represent VA SWR master.
- qcom,va-clk-mux-select VA macro MCLK MUX selection
- qcom,va-island-mode-muxsel VA macro island mode MUX selection
This property is required if qcom,va-clk-mux-select is provided
Example:
&lpass_cdc {
va_macro: va-macro {
compatible = "qcom,lpass-cdc-va-macro";
reg = <0x0C490000 0x0>;
clock-names = "va_core_clk";
clocks = <&clock_audio_va 0>;
qcom,default-clk-id = <TX_CORE_CLK>;
va-vdd-micb-supply = <&S4A>;
qcom,va-vdd-micb-voltage = <1800000 1800000>;
qcom,va-vdd-micb-current = <11200>;
qcom,va-dmic-sample-rate = <4800000>;
qcom,va-clk-mux-select = <1>;
qcom,va-island-mode-muxsel = <0x033A0000>;
qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>;
swr_2: tx_swr_master {
compatible = "qcom,swr-mstr";
wcd938x_tx_slave: wcd938x-tx-slave {
compatible = "qcom,wcd938x-slave";
};
};
};
};
RX macro in LPASS codec
Required properties:
- compatible = "qcom,lpass-cdc-rx-macro";
- reg: Specifies the Rx macro base address for LPASS
soundwire core registers.
- clock-names : clock names defined for RX macro
- clocks : clock handles defined for RX macro
- qcom,default-clk-id: Default clk ID used for RX macro
- qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
- qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order
required to be configured to receive interrupts
in BCL block of WSA macro
Example:
&lpass_cdc {
rx_macro: rx-macro {
compatible = "qcom,lpass-cdc-rx-macro";
reg = <0x62EE0000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>,
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x62C25020>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr_1: rx_swr_master {
compatible = "qcom,swr-mstr";
wcd938x_rx_slave: wcd938x-rx-slave {
compatible = "qcom,wcd938x-slave";
};
};
};
};
TX macro in LPASS codec
Required properties:
- compatible = "qcom,lpass-cdc-tx-macro";
- reg: Specifies the Tx macro base address for LPASS
soundwire core registers.
- clock-names : clock names defined for TX macro
- clocks : clock handles defined for TX macro
- qcom,tx-dmic-sample-rate: Sample rate defined for DMICs connected to TX macro
Example:
&lpass_cdc {
tx_macro: tx-macro {
compatible = "qcom,lpass-cdc-tx-macro";
reg = <0x62EC0000 0x0>;
clock-names = "tx_core_clk", "tx_npl_clk";
clocks = <&clock_audio_tx_1 0>
<&clock_audio_tx_2 0>;
qcom,tx-dmic-sample-rate = <4800000>;
};
};
Tanggu Codec
Required properties:
- compatible: "qcom,wcd937x-codec";
- qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also
corresponding master port type it need to attach.
format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>
same port_id configurations have to be grouped, and in ascending order.
- qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also
corresponding master port type it need to attach.
format: <port_id,slave_port_type, ch_mask, ch_rate, master_port_type>
same port_id configurations have to be grouped, and in ascending order.
- qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio
configuration. If this property is not defined, it is
expected to atleast define "qcom,cdc-reset-gpio" property.
- qcom,rx-slave: phandle reference of Soundwire Rx slave device.
- qcom,tx-slave: phandle reference of Soundwire Tx slave device.
Optional properties:
- cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node.
- qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV.
- qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA.
- cdc-vddio-supply: phandle of io supply's regulator device tree node.
- qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV.
- qcom,cdc-vddio-current: io supply's max current in mA.
- cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node.
- qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV.
- qcom,cdc-vdd-buck-current: buck supply's max current in mA.
- cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node.
- qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV.
- qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA.
- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
hardware probe. Supplies in this list will be
stay enabled.
- qcom,cdc-on-demand-supplies: List of supplies which can be enabled
dynamically.
Supplies in this list are off by default.
Example:
wcd937x_codec: wcd937x-codec {
compatible = "qcom,wcd937x-codec";
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
<3 DMIC5 0x8 0 DMIC7>;
qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
qcom,rx-slave = <&wcd937x_rx_slave>;
qcom,tx-slave = <&wcd937x_tx_slave>;
cdc-vdd-buck-supply = <&S4A>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-rxtx-supply = <&S4A>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
cdc-vddio-supply = <&S4A>;
qcom,cdc-vddio-voltage = <1800000 1800000>;
qcom,cdc-vddio-current = <30000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddio";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
"cdc-vdd-mic-bias";
};
Traverso Codec
Required properties:
- compatible: "qcom,wcd938x-codec";
- qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also
corresponding master port type it need to attach.
format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>
same port_id configurations have to be grouped, and in ascending order.
- qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also
corresponding master port type it need to attach.
format: <port_id,slave_port_type, ch_mask, ch_rate, master_port_type>
same port_id configurations have to be grouped, and in ascending order.
- qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio
configuration. If this property is not defined, it is
expected to atleast define "qcom,cdc-reset-gpio" property.
- qcom,rx-slave: phandle reference of Soundwire Rx slave device.
- qcom,tx-slave: phandle reference of Soundwire Tx slave device.
Optional properties:
- cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node.
- qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV.
- qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA.
- cdc-vddio-supply: phandle of io supply's regulator device tree node.
- qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV.
- qcom,cdc-vddio-current: io supply's max current in mA.
- cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node.
- qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV.
- qcom,cdc-vdd-buck-current: buck supply's max current in mA.
- cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node.
- qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV.
- qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA.
- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
hardware probe. Supplies in this list will be
stay enabled.
- qcom,cdc-on-demand-supplies: List of supplies which can be enabled
dynamically.
Supplies in this list are off by default.
Example:
wcd938x_codec: wcd938x-codec {
compatible = "qcom,wcd938x-codec";
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
<3 DMIC5 0x8 0 DMIC7>;
qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
qcom,rx-slave = <&wcd938x_rx_slave>;
qcom,tx-slave = <&wcd938x_tx_slave>;
cdc-vdd-buck-supply = <&S4A>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-rxtx-supply = <&S4A>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
cdc-vddio-supply = <&S4A>;
qcom,cdc-vddio-voltage = <1800000 1800000>;
qcom,cdc-vddio-current = <30000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddio";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck",
"cdc-vdd-mic-bias";
};
Bolero Clock Resource Manager
Required Properties:
- compatible = "qcom,bolero-clk-rsc-mngr";
- qcom,fs-gen-sequence: Register sequence for fs clock generation
- clock-names : clock names defined for WSA macro
- clocks : clock handles defined for WSA macro
Optional Properties:
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
- qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select
- qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select
Example:
&bolero {
bolero-clock-rsc-manager {
compatible = "qcom,bolero-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1>,
<0x3004 0x1>, <0x3080 0x2>;
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
qcom,va_mclk_mode_muxsel = <0x033A0000>;
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk",
"rx_npl_clk", "wsa_core_clk", "wsa_npl_clk",
"va_core_clk", "va_npl_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
};
};
LPASS Digital Codec Clock Resource Manager
Required Properties:
- compatible = "qcom,lpass-cdc-clk-rsc-mngr";
- qcom,fs-gen-sequence: Register sequence for fs clock generation
- clock-names : clock names defined for WSA macro
- clocks : clock handles defined for WSA macro
Optional Properties:
- qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select
- qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select
- qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select
Example:
&lpass_cdc {
lpass-cdc-clk-rsc-mngr {
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1>,
<0x3004 0x1>, <0x3080 0x2>;
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
qcom,va_mclk_mode_muxsel = <0x033A0000>;
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk",
"rx_npl_clk", "wsa_core_clk", "wsa_npl_clk",
"va_core_clk", "va_npl_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
};
};
WSA Analog Codec
Required Properties:
- compatible = "qcom,wsa881x-i2c-codec";
- reg: Specifies the I2C chip address.
- clock-names : clock names defined for WSA master clock
- clocks : clock handles defined for WSA master clock
- qcom,wsa-analog-clk-gpio: Specificies WSA_MCLK GPIO handle
- qcom,wsa-analog-reset-gpio: Specifies WSA reset GPIO handle
Optional Properties:
- qcom,wsa-analog-vi-gpio: Specifies WSA VI sense GPIO handle
Example:
&qupv3_se1_i2c {
wsa881x_i2c_f: wsa881x-i2c-codec@f {
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x0f>;
clock-names = "wsa_mclk";
clocks = <&wsa881x_analog_clk 0>;
qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
};
wsa881x_i2c_45: wsa881x-i2c-codec@45 {
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x045>;
};
};
WSA883x Soundwire slave device as child of Soundwire master in Bolero codec
Required properties:
- compatible = "qcom,wsa883x";
- reg: Specifies the WSA883x soundwire slave unique device address
- qcom,spkr-sd-n-gpio: speaker reset gpio
Optional properties:
- bolero-handle: phandle to bolero codec
- cdc-vdd-1p8-supply: phandle of VDD 1.8V supply's regulator device tree node.
- qcom,cdc-vdd-1p8-voltage: VDD 1.8V supply's voltage level min and max in mV.
- qcom,cdc-vdd-1p8-current: VDD 1.8V supply's max current in mA.
- qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
hardware probe. Supplies in this list will be
stay enabled.
Example:
wsa883x_0221: wsa883x@02170221 {
compatible = "qcom,wsa883x";
reg = <0x02 0x02170221>;
qcom,spkr-sd-n-gpio = <&tlmm 80 0>;
bolero-handle = <&bolero>;
cdc-vdd-1p8-supply = <&S10B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
};
Haptics Soundwire slave device as child of Soundwire master in Bolero codec
Required properties:
- compatible: "qcom,swr-haptics", or "qcom,pm8350b-swr-haptics".
- reg: Specifies the haptics soundwire slave unique device address.
- swr-slave-supply: Specify the phandle of the regulator device to take
haptics soundwire slave out of reset.
- qcom,rx_swr_ch_map: Specify the mapping of soundwire rx slave port configuration.
format: <port_id, ch_mask, ch_rate, num_ch, port_type>.
Example:
swr_haptics: swr_haptics@f0170220 {
compatible = "qcom,pm8350b-swr-haptics";
reg = <0x01 0xf0170220>;
swr-slave-supply = <&hap_swr_slave_reg>;
qcom,rx_swr_ch_map = <0 0x1 0xF 0 PCM_OUT1>;
};
SWR MIC Soundwire slave device as child of Soundwire master in digital codec
Required properties:
- compatible = "qcom,swr-dmic";
- reg: Specifies the SWR MIC soundwire slave unique device address
- qcom,swr-dmic-prefix: Prefix to use for alsa widgets and routes
- qcom,codec-name: Name for the corresponding swr mic codec
- qcom,swr-dmic-supply: Mic bias widget name that turns on this device's power supply
- qcom,wcd-handle: pHandle to wcd node that can enable this device's supply
Example:
swr_dmic_01: dmic_swr@58350220 {
compatible = "qcom,swr-dmic";
reg = <0x08 0x58350220>;
qcom,swr-dmic-prefix = "SWR_MIC0";
qcom,codec-name = "swr-dmic-01";
qcom,swr-dmic-supply = "MIC BIAS1 Standalone";
qcom,wcd-handle = <&wcd938x_codec>;
};

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&soc {
pcm0: qcom,msm-pcm {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <0>;
};
routing: qcom,msm-pcm-routing {
compatible = "qcom,msm-pcm-routing";
};
compr: qcom,msm-compr-dsp {
compatible = "qcom,msm-compr-dsp";
};
pcm1: qcom,msm-pcm-low-latency {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <1>;
qcom,msm-pcm-low-latency;
qcom,latency-level = "regular";
};
pcm2: qcom,msm-ultra-low-latency {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <2>;
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
pcm_noirq: qcom,msm-pcm-dsp-noirq {
compatible = "qcom,msm-pcm-dsp-noirq";
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
trans_loopback: qcom,msm-transcode-loopback {
compatible = "qcom,msm-transcode-loopback";
};
compress: qcom,msm-compress-dsp {
compatible = "qcom,msm-compress-dsp";
};
voip: qcom,msm-voip-dsp {
compatible = "qcom,msm-voip-dsp";
};
voice: qcom,msm-pcm-voice {
compatible = "qcom,msm-pcm-voice";
qcom,destroy-cvd;
};
stub_codec: qcom,msm-stub-codec {
compatible = "qcom,msm-stub-codec";
};
qcom,msm-dai-fe {
compatible = "qcom,msm-dai-fe";
};
afe: qcom,msm-pcm-afe {
compatible = "qcom,msm-pcm-afe";
};
dai_hdmi: qcom,msm-dai-q6-hdmi {
compatible = "qcom,msm-dai-q6-hdmi";
qcom,msm-dai-q6-dev-id = <8>;
};
dai_dp: qcom,msm-dai-q6-dp {
compatible = "qcom,msm-dai-q6-hdmi";
qcom,msm-dai-q6-dev-id = <0>;
};
dai_dp1: qcom,msm-dai-q6-dp1 {
compatible = "qcom,msm-dai-q6-hdmi";
qcom,msm-dai-q6-dev-id = <1>;
};
loopback: qcom,msm-pcm-loopback {
compatible = "qcom,msm-pcm-loopback";
};
loopback1: qcom,msm-pcm-loopback-low-latency {
compatible = "qcom,msm-pcm-loopback";
qcom,msm-pcm-loopback-low-latency;
};
pcm_dtmf: qcom,msm-pcm-dtmf {
compatible = "qcom,msm-pcm-dtmf";
};
msm_dai_mi2s: qcom,msm-dai-mi2s {
compatible = "qcom,msm-dai-mi2s";
dai_mi2s0: qcom,msm-dai-q6-mi2s-prim {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <0>;
qcom,msm-mi2s-rx-lines = <3>;
qcom,msm-mi2s-tx-lines = <0>;
};
dai_mi2s1: qcom,msm-dai-q6-mi2s-sec {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <1>;
qcom,msm-mi2s-rx-lines = <1>;
qcom,msm-mi2s-tx-lines = <0>;
};
dai_mi2s2: qcom,msm-dai-q6-mi2s-tert {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <2>;
qcom,msm-mi2s-rx-lines = <0>;
qcom,msm-mi2s-tx-lines = <3>;
};
dai_mi2s3: qcom,msm-dai-q6-mi2s-quat {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <3>;
qcom,msm-mi2s-rx-lines = <1>;
qcom,msm-mi2s-tx-lines = <2>;
};
dai_mi2s4: qcom,msm-dai-q6-mi2s-quin {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <4>;
qcom,msm-mi2s-rx-lines = <1>;
qcom,msm-mi2s-tx-lines = <2>;
};
dai_mi2s5: qcom,msm-dai-q6-mi2s-senary {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <5>;
qcom,msm-mi2s-rx-lines = <0>;
qcom,msm-mi2s-tx-lines = <3>;
};
};
msm_dai_cdc_dma: qcom,msm-dai-cdc-dma {
compatible = "qcom,msm-dai-cdc-dma";
wsa_cdc_dma_0_rx: qcom,msm-dai-wsa-cdc-dma-0-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45056>;
};
wsa_cdc_dma_0_tx: qcom,msm-dai-wsa-cdc-dma-0-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45057>;
};
wsa_cdc_dma_1_rx: qcom,msm-dai-wsa-cdc-dma-1-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45058>;
};
wsa_cdc_dma_1_tx: qcom,msm-dai-wsa-cdc-dma-1-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45059>;
};
wsa_cdc_dma_2_tx: qcom,msm-dai-wsa-cdc-dma-2-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45061>;
};
va_cdc_dma_0_tx: qcom,msm-dai-va-cdc-dma-0-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45089>;
};
va_cdc_dma_1_tx: qcom,msm-dai-va-cdc-dma-1-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45091>;
};
va_cdc_dma_2_tx: qcom,msm-dai-va-cdc-dma-2-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45093>;
};
rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45104>;
};
rx_cdc_dma_1_rx: qcom,msm-dai-rx-cdc-dma-1-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45106>;
};
rx_cdc_dma_2_rx: qcom,msm-dai-rx-cdc-dma-2-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45108>;
};
rx_cdc_dma_3_rx: qcom,msm-dai-rx-cdc-dma-3-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45110>;
};
rx_cdc_dma_4_rx: qcom,msm-dai-rx-cdc-dma-4-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45112>;
};
rx_cdc_dma_5_rx: qcom,msm-dai-rx-cdc-dma-5-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45114>;
};
rx_cdc_dma_6_rx: qcom,msm-dai-rx-cdc-dma-6-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45116>;
qcom,msm-cdc-dma-data-align = <1>;
};
rx_cdc_dma_7_rx: qcom,msm-dai-rx-cdc-dma-7-rx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45118>;
};
tx_cdc_dma_0_tx: qcom,msm-dai-tx-cdc-dma-0-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45105>;
};
tx_cdc_dma_1_tx: qcom,msm-dai-tx-cdc-dma-1-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45107>;
};
tx_cdc_dma_2_tx: qcom,msm-dai-tx-cdc-dma-2-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45109>;
};
tx_cdc_dma_3_tx: qcom,msm-dai-tx-cdc-dma-3-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45111>;
};
tx_cdc_dma_4_tx: qcom,msm-dai-tx-cdc-dma-4-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45113>;
};
tx_cdc_dma_5_tx: qcom,msm-dai-tx-cdc-dma-5-tx {
compatible = "qcom,msm-dai-cdc-dma-dev";
qcom,msm-dai-cdc-dma-dev-id = <45115>;
};
};
lsm: qcom,msm-lsm-client {
compatible = "qcom,msm-lsm-client";
};
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
sb_7_rx: qcom,msm-dai-q6-sb-7-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16398>;
qcom,msm-dai-q6-slim-dev-id = <0>;
};
sb_7_tx: qcom,msm-dai-q6-sb-7-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16399>;
qcom,msm-dai-q6-slim-dev-id = <0>;
};
sb_8_tx: qcom,msm-dai-q6-sb-8-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16401>;
qcom,msm-dai-q6-slim-dev-id = <0>;
};
bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12288>;
};
bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12289>;
};
int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12292>;
};
int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12293>;
};
afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <224>;
};
afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <225>;
};
afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <241>;
};
afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <240>;
};
incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32771>;
};
incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32772>;
};
incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32773>;
};
incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32770>;
};
afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <242>;
};
proxy_rx: qcom,msm-dai-q6-proxy-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <8194>;
};
proxy_tx: qcom,msm-dai-q6-proxy-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <8195>;
};
usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <28672>;
};
usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <28673>;
};
};
hostless: qcom,msm-pcm-hostless {
compatible = "qcom,msm-pcm-hostless";
};
audio_pkt_core_platform: qcom,audio-pkt-core-platform {
compatible = "qcom,audio-pkt-core-platform";
};
dai_pri_auxpcm: qcom,msm-pri-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "primary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_sec_auxpcm: qcom,msm-sec-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "secondary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_tert_auxpcm: qcom,msm-tert-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "tertiary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_quat_auxpcm: qcom,msm-quat-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "quaternary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_quin_auxpcm: qcom,msm-quin-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "quinary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_sen_auxpcm: qcom,msm-sen-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "senary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
hdmi_dba: qcom,msm-hdmi-dba-codec-rx {
compatible = "qcom,msm-hdmi-dba-codec-rx";
qcom,dba-bridge-chip = "adv7533";
};
adsp_loader: qcom,msm-adsp-loader {
status = "ok";
compatible = "qcom,adsp-loader";
qcom,rproc-handle = <&adsp_pas>;
qcom,adsp-state = <0>;
};
adsp_notify: qcom,msm-adsp-notify {
status = "ok";
compatible = "qcom,adsp-notify";
qcom,rproc-handle = <&adsp_pas>;
};
tdm_pri_rx: qcom,msm-dai-tdm-pri-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37120>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36864>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36864>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_pri_tx: qcom,msm-dai-tdm-pri-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37121>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36865>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36865>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_sec_rx: qcom,msm-dai-tdm-sec-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37136>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36880>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36880>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_sec_tx: qcom,msm-dai-tdm-sec-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37137>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36881>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36881>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_tert_rx: qcom,msm-dai-tdm-tert-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37152>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36896>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36896>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_tert_tx: qcom,msm-dai-tdm-tert-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37153>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36897 >;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36897 >;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_quat_rx: qcom,msm-dai-tdm-quat-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37168>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36912>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36912>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_quat_tx: qcom,msm-dai-tdm-quat-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37169>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36913 >;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36913 >;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_quin_rx: qcom,msm-dai-tdm-quin-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37184>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36928>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36928>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_quin_tx: qcom,msm-dai-tdm-quin-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37185>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36929>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36929>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_sen_rx: qcom,msm-dai-tdm-sen-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37200>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36944>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36944>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
tdm_sen_tx: qcom,msm-dai-tdm-sen-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37201>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36945>;
qcom,msm-cpudai-tdm-clk-rate = <1536000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <1>;
qcom,msm-cpudai-tdm-data-delay = <1>;
dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36945>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx {
compatible = "qcom,msm-dai-q6-spdif";
qcom,msm-dai-q6-dev-id = <20480>;
};
dai_pri_spdif_tx: qcom,msm-dai-q6-spdif-pri-tx {
compatible = "qcom,msm-dai-q6-spdif";
qcom,msm-dai-q6-dev-id = <20481>;
};
dai_sec_spdif_rx: qcom,msm-dai-q6-spdif-sec-rx {
compatible = "qcom,msm-dai-q6-spdif";
qcom,msm-dai-q6-dev-id = <20482>;
};
dai_sec_spdif_tx: qcom,msm-dai-q6-spdif-sec-tx {
compatible = "qcom,msm-dai-q6-spdif";
qcom,msm-dai-q6-dev-id = <20483>;
};
afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <24577>;
};
};

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waipio-audio-atp.dts Normal file
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/dts-v1/;
/plugin/;
#include "waipio-audio-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio ATP";
compatible = "qcom,waipio", "qcom,waipio-atp", "qcom,atp";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0x10021 0>;
};

1
waipio-audio-atp.dtsi Normal file
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@@ -0,0 +1 @@
#include "waipio-audio-overlay.dtsi"

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/dts-v1/;
/plugin/;
#include "waipio-audio-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio CDP";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0x10001 0>;
};

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#include "waipio-audio-overlay.dtsi"
&lpass_cdc {
qcom,num-macros = <4>;
};
&wsa2_macro {
status = "disabled";
};
&swr_dmic_01 {
status = "disabled";
};
&swr_dmic_02 {
status = "disabled";
};
&swr_dmic_03 {
status = "disabled";
};
&swr_dmic_04 {
status = "disabled";
};
&cdc_tert_mi2s_gpios {
status = "ok";
};
&waipio_snd {
qcom,model = "waipio-cdp-snd-card";
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"AMIC1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"AMIC2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"AMIC3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"AMIC4", "MIC BIAS3",
"AMIC5", "Analog Mic5",
"AMIC5", "MIC BIAS4",
"VA AMIC1", "Analog Mic1",
"VA AMIC1", "VA MIC BIAS1",
"VA AMIC2", "Analog Mic2",
"VA AMIC2", "VA MIC BIAS2",
"VA AMIC3", "Analog Mic3",
"VA AMIC3", "VA MIC BIAS3",
"VA AMIC4", "Analog Mic4",
"VA AMIC4", "VA MIC BIAS3",
"VA AMIC5", "Analog Mic5",
"VA AMIC5", "VA MIC BIAS4",
"TX DMIC0", "Digital Mic0",
"Digital Mic0", "MIC BIAS3",
"TX DMIC1", "Digital Mic1",
"Digital Mic1", "MIC BIAS1",
"TX DMIC2", "Digital Mic2",
"Digital Mic2", "MIC BIAS1",
"TX DMIC3", "Digital Mic3",
"Digital Mic3", "MIC BIAS3",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"Digital Mic0", "VA MIC BIAS3",
"Digital Mic1", "VA MIC BIAS1",
"Digital Mic2", "VA MIC BIAS1",
"Digital Mic3", "VA MIC BIAS3";
asoc-codec = <&stub_codec>, <&lpass_cdc>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <2>;
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
};

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/dts-v1/;
/plugin/;
#include "waipio-audio-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio MTP";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0x10008 0>;
};

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#include "waipio-audio-overlay.dtsi"
&cdc_tert_mi2s_gpios {
status = "ok";
};
&waipio_snd {
qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
};

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#include <bindings/qcom,audio-ext-clk.h>
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
#include <bindings/audio-codec-port-types.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "waipio-lpi.dtsi"
&lpass_cdc {
qcom,num-macros = <4>;
qcom,lpass-cdc-version = <6>;
#address-cells = <1>;
#size-cells = <1>;
lpass-cdc-clk-rsc-mngr {
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
qcom,wsa_mclk_mode_muxsel = <0x033A20E0>;
qcom,va_mclk_mode_muxsel = <0x03420000>;
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
"va_core_clk", "wsa2_core_clk", "rx_tx_core_clk",
"wsa_tx_core_clk", "wsa2_tx_core_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
<&clock_audio_wsa_1 0>, <&clock_audio_va_1 0>,
<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>;
};
va_macro: va-macro@33F0000 {
compatible = "qcom,lpass-cdc-va-macro";
reg = <0x33F0000 0x0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,va-dmic-sample-rate = <600000>;
qcom,va-clk-mux-select = <1>;
qcom,va-island-mode-muxsel = <0x03420000>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>;
swr2: va_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <3>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0x33b0000 0x0>;
interrupts =
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq", "swr_wake_irq";
qcom,swr-wakeup-required = <1>;
qcom,swr-num-ports = <3>;
qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,
<1 SWRM_TX1_CH2 0x2>,
<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,
<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,
<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <5>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
qcom,is-always-on = <1>;
wcd938x_tx_slave: wcd938x-tx-slave {
compatible = "qcom,wcd938x-slave";
reg = <0x0D 0x01170223>;
};
swr_dmic_04: dmic_swr@58350223 {
compatible = "qcom,swr-dmic";
reg = <0x08 0x58350223>;
qcom,swr-dmic-prefix = "SWR_MIC3";
qcom,codec-name = "swr-dmic.04";
qcom,swr-dmic-supply = <3>;
qcom,wcd-handle = <&wcd938x_codec>;
status = "disabled";
};
swr_dmic_03: dmic_swr@58350222 {
compatible = "qcom,swr-dmic";
reg = <0x08 0x58350222>;
qcom,swr-dmic-prefix = "SWR_MIC2";
qcom,codec-name = "swr-dmic.03";
qcom,swr-dmic-supply = <1>;
qcom,wcd-handle = <&wcd938x_codec>;
status = "disabled";
};
swr_dmic_02: dmic_swr@58350221 {
compatible = "qcom,swr-dmic";
reg = <0x08 0x58350221>;
qcom,swr-dmic-prefix = "SWR_MIC1";
qcom,codec-name = "swr-dmic.02";
qcom,swr-dmic-supply = <1>;
qcom,wcd-handle = <&wcd938x_codec>;
status = "disabled";
};
swr_dmic_01: dmic_swr@58350220 {
compatible = "qcom,swr-dmic";
reg = <0x08 0x58350220>;
qcom,swr-dmic-prefix = "SWR_MIC0";
qcom,codec-name = "swr-dmic.01";
qcom,swr-dmic-supply = <3>;
qcom,wcd-handle = <&wcd938x_codec>;
status = "disabled";
};
};
};
tx_macro: tx-macro@3220000 {
compatible = "qcom,lpass-cdc-tx-macro";
reg = <0x3220000 0x0>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,tx-dmic-sample-rate = <2400000>;
qcom,is-used-swr-gpio = <0>;
};
rx_macro: rx-macro@3200000 {
compatible = "qcom,lpass-cdc-rx-macro";
reg = <0x3200000 0x0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <RX_TX_CORE_CLK>;
swr1: rx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <2>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0x3210000 0x0>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <6>;
qcom,swr-port-mapping = <1 HPH_L 0x1>,
<1 HPH_R 0x2>, <2 CLSH 0x1>,
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
<4 LO 0x1>, <5 DSD_L 0x1>,
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>;
qcom,swr-num-dev = <2>;
qcom,swr-clock-stop-mode0 = <1>;
swr_haptics: swr_haptics@f0170220 {
compatible = "qcom,pm8350b-swr-haptics";
reg = <0x01 0xf0170220>;
swr-slave-supply = <&hap_swr_slave_reg>;
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
};
wcd938x_rx_slave: wcd938x-rx-slave {
compatible = "qcom,wcd938x-slave";
reg = <0x0D 0x01170224>;
};
};
};
wsa_macro: wsa-macro@3240000 {
compatible = "qcom,lpass-cdc-wsa-macro";
reg = <0x3240000 0x0>;
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
qcom,thermal-max-state = <11>;
swr0: wsa_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <1>;
qcom,mipi-sdw-block-packing-mode = <0>;
swrm-io-base = <0x3250000 0x0>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <8>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
<8 SPKR_R_VI 0x3>;
qcom,swr-num-dev = <2>;
qcom,dynamic-port-map-supported = <0>;
wsa883x_0221: wsa883x@02170221 {
compatible = "qcom,wsa883x";
reg = <0x2 0x2170221>;
qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
cdc-vdd-1p8-supply = <&S10B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "SpkrLeft";
};
wsa883x_0222: wsa883x@02170222 {
compatible = "qcom,wsa883x";
reg = <0x2 0x2170222>;
qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
cdc-vdd-1p8-supply = <&S10B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "SpkrRight";
};
};
};
wsa2_macro: wsa2-macro@31E0000 {
compatible = "qcom,lpass-cdc-wsa2-macro";
reg = <0x31E0000 0x0>;
qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
qcom,thermal-max-state = <11>;
status = "disabled";
swr3: wsa2_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <4>;
qcom,mipi-sdw-block-packing-mode = <0>;
swrm-io-base = <0x31f0000 0x0>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <8>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
<8 SPKR_R_VI 0x3>;
qcom,swr-num-dev = <2>;
qcom,dynamic-port-map-supported = <0>;
wsa883x_2_0221: wsa883x@02170221 {
compatible = "qcom,wsa883x_2";
reg = <0x2 0x2170221>;
qcom,spkr-sd-n-node = <&wsa2_spkr_en1>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
cdc-vdd-1p8-supply = <&S10B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "Spkr2Left";
};
wsa883x_2_0222: wsa883x@02170222 {
compatible = "qcom,wsa883x_2";
reg = <0x2 0x2170222>;
qcom,spkr-sd-n-node = <&wsa2_spkr_en2>;
qcom,lpass-cdc-handle = <&lpass_cdc>;
cdc-vdd-1p8-supply = <&S10B>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <20000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "Spkr2Right";
};
};
};
wcd938x_codec: wcd938x-codec {
compatible = "qcom,wcd938x-codec";
qcom,split-codec = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
qcom,swr-tx-port-params =
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
qcom,rx-slave = <&wcd938x_rx_slave>;
qcom,tx-slave = <&wcd938x_tx_slave>;
cdc-vdd-rxtx-supply = <&S10B>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
cdc-vddio-supply = <&S10B>;
qcom,cdc-vddio-voltage = <1800000 1800000>;
qcom,cdc-vddio-current = <30000>;
cdc-vdd-buck-supply = <&S10B>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-micbias4-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddio",
"cdc-vdd-buck",
"cdc-vdd-mic-bias";
};
};
&spf_core_platform {
waipio_snd: sound {
qcom,model = "waipio-mtp-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
qcom,wcn-bt = <1>;
qcom,ext-disp-audio-rx = <1>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"AMIC1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"AMIC2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"AMIC3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"AMIC4", "MIC BIAS3",
"AMIC5", "Analog Mic5",
"AMIC5", "MIC BIAS4",
"VA AMIC1", "Analog Mic1",
"VA AMIC1", "VA MIC BIAS1",
"VA AMIC2", "Analog Mic2",
"VA AMIC2", "VA MIC BIAS2",
"VA AMIC3", "Analog Mic3",
"VA AMIC3", "VA MIC BIAS3",
"VA AMIC4", "Analog Mic4",
"VA AMIC4", "VA MIC BIAS3",
"VA AMIC5", "Analog Mic5",
"VA AMIC5", "VA MIC BIAS4",
"TX DMIC0", "Digital Mic0",
"Digital Mic0", "MIC BIAS3",
"TX DMIC1", "Digital Mic1",
"Digital Mic1", "MIC BIAS3",
"TX DMIC2", "Digital Mic2",
"Digital Mic2", "MIC BIAS1",
"TX DMIC3", "Digital Mic3",
"Digital Mic3", "MIC BIAS1",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"Digital Mic0", "VA MIC BIAS3",
"Digital Mic1", "VA MIC BIAS3",
"Digital Mic2", "VA MIC BIAS1",
"Digital Mic3", "VA MIC BIAS1";
qcom,msm-mbhc-usbc-audio-supported = <0>;
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
asoc-codec = <&stub_codec>, <&lpass_cdc>,
<&wcd938x_codec>, <&swr_haptics>,
<&wsa883x_0221>, <&wsa883x_0222>;
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
"wcd938x_codec", "swr-haptics",
"wsa-codec1", "wsa-codec2";
qcom,wsa-max-devs = <2>;
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>;
qcom,cps_threshold_levels = <148 168>;
qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
qcom,cps_lower2_values = <0x0F 0x0F 0x18>;
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
<&lpass_cdc>;
};
cdc_tert_mi2s_gpios: tert_mi2s_pinctrl {
status= "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
&tert_mi2s_sd0_active>;
pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
&tert_mi2s_sd0_sleep>;
#gpio-cells = <0>;
};
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <176>;
#gpio-cells = <0>;
};
wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <181>;
#gpio-cells = <0>;
};
rx_swr_gpios: rx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
&rx_swr_data1_active>;
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
&rx_swr_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <169>;
#gpio-cells = <0>;
};
va_swr_gpios: tx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
&tx_swr_data1_active &tx_swr_data2_active>;
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <166>;
#gpio-cells = <0>;
};
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <171 172>;
#gpio-cells = <0>;
};
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <174>;
#gpio-cells = <0>;
};
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <177>;
#gpio-cells = <0>;
};
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <182>;
#gpio-cells = <0>;
};
};
&va_cdc_dma_0_tx {
qcom,msm-dai-is-island-supported = <1>;
};
&soc {
wsa_spkr_en1: wsa_spkr_en1_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};
wsa_spkr_en2: wsa_spkr_en2_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_2_sd_n_active>;
pinctrl-1 = <&spkr_2_sd_n_sleep>;
};
wsa2_spkr_en1: wsa2_spkr_en1_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr2_1_sd_n_active>;
pinctrl-1 = <&spkr2_1_sd_n_sleep>;
};
wsa2_spkr_en2: wsa2_spkr_en2_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr2_2_sd_n_active>;
pinctrl-1 = <&spkr2_2_sd_n_sleep>;
};
wcd938x_rst_gpio: msm_cdc_pinctrl@32 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wcd938x_reset_active>;
pinctrl-1 = <&wcd938x_reset_sleep>;
};
clock_audio_va_1: va_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x307>;
#clock-cells = <1>;
};
clock_audio_wsa_1: wsa_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x309>;
#clock-cells = <1>;
};
clock_audio_wsa_2: wsa2_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x310>;
#clock-cells = <1>;
};
clock_audio_rx_1: rx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30E>;
#clock-cells = <1>;
};
clock_audio_rx_tx: rx_core_tx_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x312>;
#clock-cells = <1>;
};
clock_audio_tx_1: tx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30C>;
#clock-cells = <1>;
};
clock_audio_wsa_tx: wsa_core_tx_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x314>;
#clock-cells = <1>;
};
clock_audio_wsa2_tx: wsa2_core_tx_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x316>;
#clock-cells = <1>;
};
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x318>;
#clock-cells = <1>;
};
};

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/dts-v1/;
/plugin/;
#include "waipio-audio-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD";
compatible = "qipio-qrd", "com,waipio", "qcom,qrd";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0x1000B 0>;
};

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#include "waipio-audio-overlay.dtsi"
&tx_swr_clk_active {
config {
drive-strength = <2>;
};
};
&tx_swr_data0_active {
config {
drive-strength = <2>;
};
};
&tx_swr_data1_active {
config {
drive-strength = <2>;
};
};
&tx_swr_data2_active {
config {
drive-strength = <2>;
};
};
&waipio_snd {
qcom,model = "waipio-qrd-snd-card";
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"Analog Mic2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"Analog Mic3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"Analog Mic4", "MIC BIAS3",
"AMIC5", "Analog Mic5",
"Analog Mic5", "MIC BIAS4",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"HAP_IN", "PCM_OUT",
"WSA SRC0_INP", "SRC0",
"WSA_TX DEC0_INP", "TX DEC0 MUX",
"WSA_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK";
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
};

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/dts-v1/;
/plugin/;
#include "waipio-audio-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio RUMI";
compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";;
qcom,msm-id = <457 0x10000>;
qcom,board-id = <15 0>;
};

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#include "waipio-audio-overlay.dtsi"
&waipio_snd {
compatible = "qcom,waipio-asoc-snd-stub";
asoc-codec = <&stub_codec>;
asoc-codec-names = "msm-stub-codec.1";
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,waipio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include "waipio-audio.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v1 SoC";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x10000>, <482 0x10000>;
qcom,board-id = <0 0>;
};

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#include <bindings/qcom,audio-ext-clk.h>
#include <bindings/qcom,gpr.h>
#include "msm-audio-lpass.dtsi"
&soc {
spf_core_platform: spf_core_platform {
compatible = "qcom,spf-core-platform";
};
lpass_core_hw_vote: vote_lpass_core_hw {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
#clock-cells = <1>;
};
lpass_audio_hw_vote: vote_lpass_audio_hw {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
#clock-cells = <1>;
};
};
&glink_edge {
audio_gpr: qcom,gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,intents = <0x200 20>;
reg = <GPR_DOMAIN_ADSP>;
spf_core {
compatible = "qcom,spf_core";
reg = <GPR_SVC_ADSP_CORE>;
};
audio-pkt {
compatible = "qcom,audio-pkt";
qcom,audiopkt-ch-name = "apr_audio_svc";
reg = <GPR_SVC_MAX>;
};
audio_prm: q6prm {
compatible = "qcom,audio_prm";
reg = <GPR_SVC_ASM>;
};
};
};
&spf_core_platform {
msm_audio_ion: qcom,msm-audio-ion {
compatible = "qcom,msm-audio-ion";
qcom,smmu-version = <2>;
qcom,smmu-enabled;
iommus = <&apps_smmu 0x1801 0x0>;
qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
dma-coherent;
};
msm_audio_ion_cma: qcom,msm-audio-ion-cma {
compatible = "qcom,msm-audio-ion-cma";
};
lpi_tlmm: lpi_pinctrl@3440000 {
compatible = "qcom,lpi-pinctrl";
reg = <0x3440000 0x0>;
qcom,slew-reg = <0x34da000 0x0>;
qcom,gpios-count = <23>;
gpio-controller;
#gpio-cells = <2>;
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
<0x00002000>, <0x00003000>,
<0x00004000>, <0x00005000>,
<0x00006000>, <0x00007000>,
<0x00008000>, <0x00009000>,
<0x0000A000>, <0x0000B000>,
<0x0000C000>, <0x0000D000>,
<0x0000E000>, <0x0000F000>,
<0x00010000>, <0x00011000>,
<0x00012000>, <0x00013000>,
<0x00014000>, <0x00015000>,
<0x00016000>;
qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
<0x00000004>, <0x00000008>,
<0x0000000A>, <0x0000000C>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000010>, <0x00000012>,
<0x00000000>, <0x00000000>,
<0x00000006>, <0x00000014>,
<0x00000016>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000000>;
clock-names = "lpass_core_hw_vote";
clocks = <&lpass_core_hw_vote 0>;
};
lpass_cdc: lpass-cdc {
compatible = "qcom,lpass-cdc";
clock-names = "lpass_core_hw_vote",
"lpass_audio_hw_vote";
clocks = <&lpass_core_hw_vote 0>,
<&lpass_audio_hw_vote 0>;
lpass-cdc-clk-rsc-mngr {
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
};
va_macro: va-macro@33F0000 {
swr2: va_swr_master {
};
};
tx_macro: tx-macro@3220000 {
};
rx_macro: rx-macro@3200000 {
swr1: rx_swr_master {
};
};
wsa_macro: wsa-macro@3240000 {
swr0: wsa_swr_master {
};
};
wsa2_macro: wsa2-macro@31E0000 {
swr3: wsa2_swr_master {
};
};
};
waipio_snd: sound {
compatible = "qcom,waipio-asoc-snd";
qcom,mi2s-audio-intf = <1>;
qcom,auxpcm-audio-intf = <1>;
qcom,wcn-bt = <0>;
qcom,ext-disp-audio-rx = <0>;
qcom,afe-rxtx-lb = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
fsa4480-i2c-handle = <&fsa4480>;
};
};
&aliases {
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@3240000/wsa_swr_master";
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@3200000/rx_swr_master";
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@33F0000/va_swr_master";
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@31E0000/wsa2_swr_master";
};

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