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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
f976cab7ac
Add an SPMI PMIC arbiter device so that it is possible to communicate with PMICs attached to the SPMI bus and also add top level slave devices and their peripherals. Change-Id: I15afa13ed9edfd455c1594ada1a80748d844c149
234 lines
5.2 KiB
Plaintext
234 lines
5.2 KiB
Plaintext
#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/input/qcom,qpnp-power-on.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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&spmi_bus {
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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pm8775_1: qcom,pm8775@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8775_1_tz: qcom,temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pon_pbs@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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qcom,system-reset;
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qcom,store-hard-reset-reason;
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};
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pon_hlos@1200 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x1200>, <0x800>;
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reg-names = "pon_hlos", "pon_pbs";
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interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>,
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<0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>;
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interrupt-names = "kpdpwr", "resin";
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qcom,kpdpwr-sw-debounce;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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linux,code = <KEY_POWER>;
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};
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qcom,pon_2 {
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qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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pm8775_1_clkdiv: clock-controller@5700 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5700>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8775_1_div_clk1",
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"pm8775_1_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8775_1_rtc: qcom,pm8775_1_rtc {
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compatible = "qcom,pmk8350-rtc";
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reg = <0x6100>, <0x6200>;
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reg-names = "rtc", "alarm";
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interrupts = <0x0 0x62 0x1 IRQ_TYPE_NONE>;
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};
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pm8775_1_gpios: pinctrl@8800 {
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compatible = "qcom,pm8775-gpio";
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reg = <0x8800>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pm8775_1_sdam_2: sdam@7100 {
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compatible = "qcom,spmi-sdam";
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reg = <0x7100>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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pm8775_1_sdam_5: sdam@7400 {
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compatible = "qcom,spmi-sdam";
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reg = <0x7400>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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/* below definitions are for the second instance of pm8775 */
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pm8775_2: qcom,pm8775@2 {
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compatible = "qcom,spmi-pmic";
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reg = <2 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8775_2_tz: qcom,temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pon_pbs@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pon_hlos@1200 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x1200>, <0x800>;
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reg-names = "pon_hlos", "pon_pbs";
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};
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pm8775_2_clkdiv: clock-controller@5700 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5700>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8775_2_div_clk1",
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"pm8775_2_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8775_2_gpios: pinctrl@8800 {
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compatible = "qcom,pm8775-gpio";
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reg = <0x8800>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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/* below definitions are for the third instance of pm8775 */
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pm8775_3: qcom,pm8775@4 {
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compatible = "qcom,spmi-pmic";
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reg = <4 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8775_3_tz: qcom,temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pon_pbs@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pon_hlos@1200 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x1200>, <0x800>;
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reg-names = "pon_hlos", "pon_pbs";
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};
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pm8775_3_clkdiv: clock-controller@5700 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5700>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8775_3_div_clk1",
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"pm8775_3_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8775_3_gpios: pinctrl@8800 {
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compatible = "qcom,pm8775-gpio";
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reg = <0x8800>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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/* below definitions are for the fourth instance of pm8775 */
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pm8775_4: qcom,pm8775@6 {
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compatible = "qcom,spmi-pmic";
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reg = <6 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8775_4_tz: qcom,temp-alarm@a00 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0xa00>;
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interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
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#thermal-sensor-cells = <0>;
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};
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pon_pbs@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pon_hlos@1200 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x1200>, <0x800>;
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reg-names = "pon_hlos", "pon_pbs";
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};
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pm8775_4_clkdiv: clock-controller@5700 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5700>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8775_4_div_clk1",
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"pm8775_4_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8775_4_gpios: pinctrl@8800 {
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compatible = "qcom,pm8775-gpio";
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reg = <0x8800>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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