mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
f63ea151cf
Add the support for debug clock controller node for SDXPINN platform. Change-Id: I17edde591410b356bba0736721924f534d6d1112
826 lines
19 KiB
Plaintext
826 lines
19 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDXPINN";
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compatible = "qcom,sdxpinn";
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qcom,msm-id = <556 0x10000>, <580 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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chosen: chosen { };
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aliases {
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serial0 = &qupv3_se1_2uart;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90f00000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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SILVER_OFF: silver-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <235>;
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exit-latency-us = <428>;
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min-residency-us = <1774>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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SILVER_RAIL_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <800>;
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exit-latency-us = <750>;
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min-residency-us = <4090>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_PWR_DN: cluster-d4 { /* D4 */
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compatible = "domain-idle-state";
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idle-state-name = "l3-off";
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entry-latency-us = <1050>;
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exit-latency-us = <2500>;
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min-residency-us = <5309>;
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arm,psci-suspend-param = <0x41000044>;
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};
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CX_RET: cx-ret { /* Cx Ret */
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compatible = "domain-idle-state";
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idle-state-name = "cx-ret";
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entry-latency-us = <2761>;
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exit-latency-us = <3964>;
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min-residency-us = <8467>;
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arm,psci-suspend-param = <0x41001344>;
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};
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APSS_OFF: cluster-e3 { /* E3 */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <2793>;
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exit-latency-us = <4023>;
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min-residency-us = <9826>;
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arm,psci-suspend-param = <0x4100B344>;
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};
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};
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soc: soc { };
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};
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#include "sdxpinn-reserved-memory.dtsi"
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>;
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};
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};
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>,/* GICD */
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<0x17260000 0x80000>;/* GICR * 4 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apps_rsc: rsc@17a00000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17a00000 0x10000>,
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<0x17a10000 0x10000>,
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<0x17a20000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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qcom,drv-count = <3>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&CLUSTER_PD>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 3>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 1>;
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};
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rpmhcc: clock-controller {
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compatible = "qcom,sdxpinn-rpmh-clk";
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#clock-cells = <1>;
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};
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};
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};
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cpuss-sleep-stats@17800054 {
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compatible = "qcom,cpuss-sleep-stats-v2";
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reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
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<0x17830054 0x4>, <0x17880098 0x4>, <0x178c0000 0x10000>;
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reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
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"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
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"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
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num-cpus = <4>;
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};
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soc-sleep-stats@c3f0000 {
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compatible = "qcom,rpmh-sleep-stats";
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reg = <0xc3f0000 0x400>;
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ss-name = "modem", "adsp", "apss";
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};
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subsystem-sleep-stats@c3f0000 {
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compatible = "qcom,subsystem-sleep-stats";
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reg = <0xc3f0000 0x400>;
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};
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tcsr_mutex_block: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x1f40000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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qcom,smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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aoss_qmp: power-controller@c300000 {
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compatible = "qcom,sdxpinn-aoss-qmp";
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reg = <0xc300000 0x400>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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#power-domain-cells = <1>;
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#clock-cells = <0>;
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};
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qmp_aop: qcom,qmp-aop {
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compatible = "qcom,qmp-mbox";
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qcom,qmp = <&aoss_qmp>;
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label = "aop";
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#mbox-cells = <1>;
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};
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qmp_tme: qcom,qmp-tme {
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compatible = "qcom,qmp-mbox";
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qcom,remote-pid = <14>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "tme_qmp";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "tme";
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qcom,early-boot;
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priority = <0>;
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mbox-desc-offset = <0x0>;
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#mbox-cells = <1>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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cluster-device {
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compatible = "qcom,lpm-cluster-dev";
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power-domains = <&CLUSTER_PD>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sdxpinn-pdc", "qcom,pdc";
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reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
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qcom,pdc-ranges = <0 147 52>, <52 558 91>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie20_phy_aux_clk: pcie20_phy_aux_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie20_phy_aux_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie_1_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_2_pipe_clk: pcie_2_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_2_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_pipe_clk: pcie_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gcc: clock-controller@80000 {
|
|
compatible = "qcom,sdxpinn-gcc", "syscon";
|
|
reg = <0x80000 0x1f4200>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&pcie20_phy_aux_clk>,
|
|
<&pcie_1_pipe_clk>,
|
|
<&pcie_2_pipe_clk>,
|
|
<&pcie_pipe_clk>,
|
|
<&sleep_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"pcie20_phy_aux_clk",
|
|
"pcie_1_pipe_clk",
|
|
"pcie_2_pipe_clk",
|
|
"pcie_pipe_clk",
|
|
"sleep_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@17aa0000 {
|
|
compatible = "syscon";
|
|
reg = <0x17aa0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@190ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x190ba000 0x54>;
|
|
};
|
|
|
|
debugcc: clock-controller@0 {
|
|
compatible = "qcom,sdxpinn-debugcc";
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,gcc = <&gcc>;
|
|
qcom,mccc = <&mccc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc 0>;
|
|
clock-names = "xo_clk_src",
|
|
"gcc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
gcc_emac0_gdsc: qcom,gdsc@f1004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xf1004 0x4>;
|
|
regulator-name = "gcc_emac0_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_emac1_gdsc: qcom,gdsc@f2004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xf2004 0x4>;
|
|
regulator-name = "gcc_emac1_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_1_gdsc: qcom,gdsc@e7004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xe7004 0x4>;
|
|
regulator-name = "gcc_pcie_1_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xd6004 0x4>;
|
|
regulator-name = "gcc_pcie_1_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_2_gdsc: qcom,gdsc@e8004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xe8004 0x4>;
|
|
regulator-name = "gcc_pcie_2_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xee004 0x4>;
|
|
regulator-name = "gcc_pcie_2_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_gdsc: qcom,gdsc@d3004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xd3004 0x4>;
|
|
regulator-name = "gcc_pcie_gdsc";
|
|
parent-supply = <&VDD_MXA_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_pcie_phy_gdsc: qcom,gdsc@d4004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xd4004 0x4>;
|
|
regulator-name = "gcc_pcie_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
gcc_usb30_gdsc: qcom,gdsc@a7004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xa7004 0x4>;
|
|
regulator-name = "gcc_usb30_gdsc";
|
|
parent-supply = <&VDD_MXA_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_usb3_phy_gdsc: qcom,gdsc@a8008 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xa8008 0x4>;
|
|
regulator-name = "gcc_usb3_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
qnand_1: nand@1c98000 {
|
|
compatible = "qcom,msm-nand";
|
|
reg = <0x01c98000 0x1000>,
|
|
<0x01c9C000 0x1c000>;
|
|
reg-names = "nand_phys",
|
|
"bam_phys";
|
|
qcom,reg-adjustment-offset = <0x4000>;
|
|
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "bam_irq";
|
|
|
|
clock-names = "core_clk";
|
|
clocks = <&rpmhcc RPMH_QPIC_CLK>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,sdxpinn-pinctrl";
|
|
reg = <0x0F000000 0x400000>;
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
wakeup-parent = <&pdc>;
|
|
};
|
|
|
|
ipcc_mproc: qcom,ipcc@408000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x408000 0x1000>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@c42d000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc42d000 0x4000>,
|
|
<0xc400000 0x2800>,
|
|
<0xc500000 0x200000>,
|
|
<0xc440000 0x3c000>,
|
|
<0xc4c0000 0x10000>;
|
|
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
qcom,bus-id = <0>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
|
|
pcie_ep: qcom,pcie@0x48000000 {
|
|
compatible = "qcom,pcie-ep";
|
|
reg = <0x48003800 0x1000>,
|
|
<0x48000000 0xf20>,
|
|
<0x48000f20 0xa8>,
|
|
<0x48001000 0x2000>,
|
|
<0x01bf0000 0x4000>,
|
|
<0x01bf7000 0x2000>,
|
|
<0x01bf4000 0x1000>,
|
|
<0x01fcb000 0x1000>,
|
|
<0x0c2fa000 0x4>;
|
|
reg-names = "msi", "dm_core", "elbi", "iatu",
|
|
"parf", "phy", "mmio", "tcsr_pcie_perst_en",
|
|
"aoss_cc_reset";
|
|
|
|
#address-cells = <0>;
|
|
interrupt-parent = <&pcie_ep>;
|
|
interrupts = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0xffffffff>;
|
|
interrupt-map = <0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int_global";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie_ep_clkreq_default
|
|
&pcie_ep_perst_default
|
|
&pcie_ep_wake_default>;
|
|
clkreq-gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
|
|
perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
|
|
wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
|
|
|
gdsc-vdd-supply = <&gcc_pcie_gdsc>;
|
|
gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>;
|
|
vreg-1p8-supply = <&L1B>;
|
|
vreg-0p9-supply = <&L4B>;
|
|
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
|
qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>;
|
|
qcom,vreg-0p9-voltage-level = <912000 880000 177000>;
|
|
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
0>;
|
|
|
|
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_SLEEP_CLK>,
|
|
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_PCIE_PIPE_CLK_SRC>,
|
|
<&pcie_pipe_clk>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
|
|
clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk",
|
|
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
|
"pcie_aux_clk", "pcie_ldo",
|
|
"pcie_sleep_clk",
|
|
"pcie_slv_q2a_axi_clk",
|
|
"pcie_pipe_clk_mux",
|
|
"pcie_pipe_clk_ext_src",
|
|
"pcie_0_ref_clk_src";
|
|
|
|
resets = <&gcc GCC_PCIE_BCR>,
|
|
<&gcc GCC_PCIE_PHY_BCR>;
|
|
|
|
reset-names = "pcie_core_reset",
|
|
"pcie_phy_reset";
|
|
qcom,pcie-vendor-id = /bits/ 16 <0x17cb>;
|
|
qcom,pcie-device-id = /bits/ 16 <0x0309>;
|
|
qcom,pcie-link-speed = <4>;
|
|
qcom,pcie-phy-ver = <7>;
|
|
qcom,pcie-active-config;
|
|
qcom,pcie-aggregated-irq;
|
|
qcom,pcie-mhi-a7-irq;
|
|
qcom,phy-status-reg2 = <0x1214>;
|
|
qcom,mhi-soc-reset-offset = <0xb01b8>;
|
|
qcom,aoss-rst-clr;
|
|
qcom,aux-clk = <0x13>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mhi_device: mhi_dev@1bf4000 {
|
|
compatible = "qcom,msm-mhi-dev";
|
|
reg = <0x1bf4000 0x1000>;
|
|
reg-names = "mhi_mmio_base";
|
|
qcom,mhi-ep-msi = <0>;
|
|
qcom,mhi-version = <0x1000000>;
|
|
qcom,use-mhi-dma-software-channel;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mhi-device-inta";
|
|
qcom,mhi-ifc-id = <0x030917cb>;
|
|
qcom,mhi-interrupt;
|
|
qcom,no-m0-timeout;
|
|
status = "disabled";
|
|
};
|
|
|
|
mhi_net_device: qcom,mhi_net_dev {
|
|
compatible = "qcom,msm-mhi-dev-net";
|
|
status = "disabled";
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
};
|
|
|
|
#include "ipcc-test-sdxpinn.dtsi"
|
|
#include "sdxpinn-regulators.dtsi"
|
|
#include "sdxpinn-coresight.dtsi"
|
|
#include "sdxpinn-debug.dtsi"
|
|
#include "sdxpinn-pinctrl.dtsi"
|
|
#include "sdxpinn-pcie.dtsi"
|
|
#include "sdxpinn-usb.dtsi"
|
|
#include "sdxpinn-qupv3.dtsi"
|
|
#include "msm-arm-smmu-sdxpinn.dtsi"
|
|
#include "sdxpinn-dma-heaps.dtsi"
|
|
|
|
&qupv3_se1_2uart {
|
|
status = "ok";
|
|
};
|