mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
dc2e5b85a1
Some endpoints like NVMe D3cold transition is prohibited as it decreases the life time of the device (D3 cold is treated as power cycle). So turning off the link during S3 can reduce life span of the NVMe. For those endpoints adding a flag to inform the driver that APSS based l1ss-sleep is supported. The PCIe driver will keep the link in L1ss and turn off PCIe resources if this flag is set. Change-Id: I3682bda297181eb9f5b63cf817b05e37b160b3ce
40 lines
736 B
Plaintext
40 lines
736 B
Plaintext
#include "kalama-qrd.dtsi"
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&sdhc_2 {
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cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>;
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};
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&usb_qmp_dp_phy {
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pinctrl-names = "default";
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};
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&redriver {
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status = "disabled";
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};
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®ulator_ocp_notifier {
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/delete-property/ periph-bc3-supply;
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/delete-property/ periph-bc4-supply;
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/delete-property/ periph-bc5-supply;
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/delete-property/ periph-bc6-supply;
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/delete-property/ periph-bc7-supply;
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};
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&pm8550b_eusb2_repeater {
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qcom,param-override-seq =
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/* <value reg_offset> */
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/* Adjust HS trasmit amplitude */
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<0xb 0x51
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/* Squelch detection threshold */
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0x3 0x54
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/* Tx pre-emphasis tuning */
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0x3 0x57
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/* HS disconnect threshold */
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0x6 0x53>;
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};
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&pcie1 {
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qcom,boot-option = <0x2>;
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qcom,apss-based-l1ss-sleep;
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};
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