mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
ed58658486
Add support for all the clock controllers and also add gdsc regulators. Change-Id: I0ad222f8724cf6ff9a2ec9e181f7de11e3cf82a2
973 lines
22 KiB
Plaintext
973 lines
22 KiB
Plaintext
#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-lemans.h>
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#include <dt-bindings/clock/qcom,dispcc-lemans.h>
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#include <dt-bindings/clock/qcom,gcc-lemans.h>
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#include <dt-bindings/clock/qcom,gpucc-lemans.h>
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#include <dt-bindings/clock/qcom,videocc-lemans.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Lemans";
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compatible = "qcom,lemans";
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qcom,msm-id = <532 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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chosen: chosen { };
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aliases { };
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soc: soc { };
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firmware: firmware { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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cache-size = <0x200000>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@10000 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_1>;
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L3_1: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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cache-size = <0x200000>;
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};
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};
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};
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CPU5: cpu@10100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_1>;
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};
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};
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CPU6: cpu@10200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10200>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_1>;
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};
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};
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CPU7: cpu@10300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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next-level-cache = <&L3_1>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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};
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&firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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sail_ss_mem: sail_ss_region@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x10000000>;
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};
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hyp_mem: hyp_region@90000000 {
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no-map;
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reg = <0x0 0x90000000 0x0 0x600000>;
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};
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xbl_boot_mem: xbl_boot_region@90600000 {
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no-map;
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reg = <0x0 0x90600000 0x0 0x200000>;
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};
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aop_image_mem: aop_image_region@90800000 {
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no-map;
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reg = <0x0 0x90800000 0x0 0x60000>;
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};
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aop_cmd_db_mem: aop_cmd_db_region@90860000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x0 0x90860000 0x0 0x20000>;
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};
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uefi_log: uefi_log_region@908b0000 {
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no-map;
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reg = <0x0 0x908b0000 0x0 0x10000>;
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};
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reserved_mem: reserved_region@908f0000 {
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no-map;
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reg = <0x0 0x908f0000 0x0 0xf000>;
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};
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secdata_apss_mem: secdata_apss_region@908ff000 {
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no-map;
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reg = <0x0 0x908ff000 0x0 0x1000>;
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};
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smem_mem: smem_region@90900000 {
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no-map;
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reg = <0x0 0x90900000 0x0 0x200000>;
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};
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cpucp_fw_mem: cpucp_fw_region@90b00000 {
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no-map;
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reg = <0x0 0x90b00000 0x0 0x100000>;
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};
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lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 {
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no-map;
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reg = <0x0 0x93b00000 0x0 0xf00000>;
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};
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adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 {
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no-map;
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reg = <0x0 0x94a00000 0x0 0x800000>;
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};
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pil_camera_mem: pil_camera_region@95200000 {
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no-map;
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reg = <0x0 0x95200000 0x0 0x500000>;
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};
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pil_adsp_mem: pil_adsp_region@95c00000 {
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no-map;
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reg = <0x0 0x95c00000 0x0 0x1e00000>;
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};
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pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
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no-map;
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reg = <0x0 0x97b00000 0x0 0x1e00000>;
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};
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pil_gdsp1_mem: pil_gdsp1_region@99900000 {
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no-map;
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reg = <0x0 0x99900000 0x0 0x1e00000>;
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};
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pil_cdsp0_mem: pil_cdsp0_region@9b800000 {
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no-map;
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reg = <0x0 0x9b800000 0x0 0x1e00000>;
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};
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pil_gpu_mem: pil_gpu_region@9d600000 {
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no-map;
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reg = <0x0 0x9d600000 0x0 0x2000>;
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};
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pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
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no-map;
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reg = <0x0 0x9d700000 0x0 0x1e00000>;
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};
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pil_cvp_mem: pil_cvp_region@9f500000 {
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no-map;
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reg = <0x0 0x9f500000 0x0 0x700000>;
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};
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pil_video_mem: pil_video_region@9fc00000 {
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no-map;
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reg = <0x0 0x9fc00000 0x0 0x700000>;
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};
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hyptz_reserved_mem: hyptz_reserved_region@beb00000 {
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no-map;
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reg = <0x0 0xbeb00000 0x0 0x11500000>;
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};
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tz_stat_mem: tz_stat_region@d0000000 {
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no-map;
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reg = <0x0 0xd0000000 0x0 0x100000>;
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};
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tags_mem: tags_region@d0100000 {
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no-map;
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reg = <0x0 0xd0100000 0x0 0x1200000>;
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};
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qtee_mem: qtee_region@d1300000 {
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no-map;
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reg = <0x0 0xd1300000 0x0 0x500000>;
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};
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trusted_apps_mem: trusted_apps_region@d1800000 {
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no-map;
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reg = <0x0 0xd1800000 0x0 0x3900000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x3000000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,lemans-pdc", "qcom,pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
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qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
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<55 306 4>, <59 312 3>, <62 374 2>,
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<64 434 2>, <66 438 2>, <70 520 1>,
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<73 523 1>, <118 568 6>, <124 609 3>,
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<159 638 1>, <160 720 3>, <169 728 30>,
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<199 416 2>, <201 449 1>, <202 89 1>,
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<203 451 1>, <204 462 1>, <205 264 1>,
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<206 579 1>, <207 653 1>, <208 656 1>,
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<209 659 1>, <210 122 1>, <211 699 1>,
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<212 705 1>, <213 450 1>, <214 643 2>,
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<216 646 5>, <221 390 5>, <226 700 2>,
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<228 440 1>, <229 663 1>, <230 524 2>,
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<232 612 3>, <235 723 5>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x18200000 0x10000>,
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<0x18210000 0x10000>,
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<0x18220000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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qcom,drv-count = <3>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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rpmhcc: qcom,rpmhcc {
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compatible = "qcom,lemans-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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status = "okay";
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};
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,msm-imem@146d8000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146d8000 0x1000>;
|
|
ranges = <0x0 0x146d8000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_1_pipe_clk: pcie_1_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_phy_aux_clk: pcie_phy_aux_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_phy_aux_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rxc0_ref_clk: rxc0_ref_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "rxc0_ref_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rxc1_ref_clk: rxc1_ref_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "rxc0_ref_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_card_rx_symbol_0_clk: ufs_card_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_card_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_card_rx_symbol_1_clk: ufs_card_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_card_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_card_tx_symbol_0_clk: ufs_card_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_card_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_sec_pipe_clk: usb3_phy_wrapper_gcc_usb30_sec_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,lemans-gcc", "syscon";
|
|
reg = <0x100000 0xc7018>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
|
|
<&pcie_phy_aux_clk>, <&rxc0_ref_clk>, <&rxc1_ref_clk>, <&sleep_clk>,
|
|
<&ufs_card_rx_symbol_0_clk>, <&ufs_card_rx_symbol_1_clk>,
|
|
<&ufs_card_tx_symbol_0_clk>, <&ufs_phy_rx_symbol_0_clk>,
|
|
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>;
|
|
clock-names = "bi_tcxo", "pcie_0_pipe_clk", "pcie_1_pipe_clk",
|
|
"pcie_phy_aux_clk", "rxc0_ref_clk", "rxc1_ref_clk", "sleep_clk",
|
|
"ufs_card_rx_symbol_0_clk", "ufs_card_rx_symbol_1_clk",
|
|
"ufs_card_tx_symbol_0_clk", "ufs_phy_rx_symbol_0_clk",
|
|
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_prim_pipe_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,lemans-camcc", "syscon";
|
|
reg = <0xade0000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
|
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_CAMERA_AHB_CLK>, <&sleep_clk>;
|
|
clock-names = "bi_tcxo", "iface", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc0: clock-controller@af00000 {
|
|
compatible = "qcom,lemans-dispcc0", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc1: clock-controller@22100000 {
|
|
compatible = "qcom,lemans-dispcc1", "syscon";
|
|
reg = <0x22100000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>, <&gcc GCC_DISP1_AHB_CLK>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,lemans-gpucc", "syscon";
|
|
reg = <0x3d90000 0xa000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo", "iface", "gpll0_out_main", "gpll0_out_main_div";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@abf0000 {
|
|
compatible = "qcom,lemans-videocc", "syscon";
|
|
reg = <0xabf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>, <&sleep_clk>;
|
|
clock-names = "bi_tcxo", "iface", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: qcom,cpufreq-hw@18591000 {
|
|
compatible = "qcom,cpufreq-hw-epss";
|
|
reg = <0x18591000 0x1000>, <0x18593000 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
qcom,skip-enable-check;
|
|
qcom,lut-row-size = <4>;
|
|
#freq-domain-cells = <2>;
|
|
};
|
|
|
|
qcom,cpufreq-hw-debug@18591000 {
|
|
compatible = "qcom,cpufreq-hw-epss-debug";
|
|
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
|
|
};
|
|
|
|
apsscc: syscon@182a0000 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@90ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x90ba000 0x54>;
|
|
};
|
|
|
|
debugcc: debug-clock-controller@0 {
|
|
compatible = "qcom,lemans-debugcc";
|
|
qcom,gcc = <&gcc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc0 = <&dispcc0>;
|
|
qcom,dispcc1 = <&dispcc1>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,videocc = <&videocc>;
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,mccc = <&mccc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo_clk_src";
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
#include "lemans-4pmic-regulators.dtsi"
|
|
#include "lemans-gdsc.dtsi"
|
|
|
|
&cam_cc_titan_top_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&disp0_cc_mdss_core_gdsc {
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&disp0_cc_mdss_core_int2_gdsc {
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&disp1_cc_mdss_core_gdsc {
|
|
clocks = <&gcc GCC_DISP1_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&disp1_cc_mdss_core_int2_gdsc {
|
|
clocks = <&gcc GCC_DISP1_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_emac0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_emac1_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_1_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_card_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb20_prim_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_sec_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu2_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu3_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc {
|
|
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_gx_gdsc {
|
|
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_GX_MXC_VOTER_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0c_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs1_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs1c_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
status = "ok";
|
|
};
|