mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
ARM: dts: msm: Add clock controllers and gdscs for lemans
Add support for all the clock controllers and also add gdsc regulators. Change-Id: I0ad222f8724cf6ff9a2ec9e181f7de11e3cf82a2
This commit is contained in:
Veera Vegivada
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
f97f85676f
commit
ed58658486
296
qcom/lemans-gdsc.dtsi
Normal file
296
qcom/lemans-gdsc.dtsi
Normal file
@@ -0,0 +1,296 @@
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&soc {
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/* CAM_CC GDSCs */
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cam_cc_titan_top_gdsc: qcom,gdsc@adf31bc {
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compatible = "qcom,gdsc";
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reg = <0xadf31bc 0x4>;
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regulator-name = "cam_cc_titan_top_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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/* DISP_CC_0 GDSCs */
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disp0_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
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compatible = "qcom,gdsc";
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reg = <0xaf09000 0x4>;
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regulator-name = "disp0_cc_mdss_core_gdsc";
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qcom,retain-regs;
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qcom,support-hw-trigger;
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proxy-supply = <&disp0_cc_mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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disp0_cc_mdss_core_int2_gdsc: qcom,gdsc@af0d000 {
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compatible = "qcom,gdsc";
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reg = <0xaf0d000 0x4>;
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regulator-name = "disp0_cc_mdss_core_int2_gdsc";
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parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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proxy-supply = <&disp0_cc_mdss_core_int2_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* DISP_CC_1 GDSCs */
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disp1_cc_mdss_core_gdsc: qcom,gdsc@22109000 {
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compatible = "qcom,gdsc";
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reg = <0x22109000 0x4>;
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regulator-name = "disp1_cc_mdss_core_gdsc";
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parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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proxy-supply = <&disp1_cc_mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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disp1_cc_mdss_core_int2_gdsc: qcom,gdsc@2210d000 {
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compatible = "qcom,gdsc";
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reg = <0x2210d000 0x4>;
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regulator-name = "disp1_cc_mdss_core_int2_gdsc";
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parent-supply = <&VDD_MM_LEVEL>;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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proxy-supply = <&disp1_cc_mdss_core_int2_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GCC GDSCs */
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gcc_emac0_gdsc: qcom,gdsc@1b6004 {
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compatible = "qcom,gdsc";
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reg = <0x1b6004 0x4>;
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regulator-name = "gcc_emac0_gdsc";
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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gcc_emac1_gdsc: qcom,gdsc@1b4004 {
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compatible = "qcom,gdsc";
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reg = <0x1b4004 0x4>;
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regulator-name = "gcc_emac1_gdsc";
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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gcc_apcs_gdsc_vote_ctrl: syscon@14b104 {
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compatible = "syscon";
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reg = <0x14b104 0x4>;
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};
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gcc_pcie_0_gdsc: qcom,gdsc@1a9004 {
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compatible = "qcom,gdsc";
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reg = <0x1a9004 0x4>;
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regulator-name = "gcc_pcie_0_gdsc";
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
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qcom,no-status-check-on-disable;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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gcc_pcie_1_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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reg = <0x177004 0x4>;
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regulator-name = "gcc_pcie_1_gdsc";
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
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qcom,no-status-check-on-disable;
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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gcc_ufs_card_gdsc: qcom,gdsc@181004 {
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compatible = "qcom,gdsc";
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reg = <0x181004 0x4>;
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regulator-name = "gcc_ufs_card_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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gcc_ufs_phy_gdsc: qcom,gdsc@183004 {
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compatible = "qcom,gdsc";
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reg = <0x183004 0x4>;
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regulator-name = "gcc_ufs_phy_gdsc";
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qcom,gds-timeout = <1500>;
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qcom,retain-regs;
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status = "disabled";
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};
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gcc_usb20_prim_gdsc: qcom,gdsc@11c004 {
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compatible = "qcom,gdsc";
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reg = <0x11c004 0x4>;
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regulator-name = "gcc_usb20_prim_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@11b004 {
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compatible = "qcom,gdsc";
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reg = <0x11b004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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gcc_usb30_sec_gdsc: qcom,gdsc@12f004 {
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compatible = "qcom,gdsc";
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reg = <0x12f004 0x4>;
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regulator-name = "gcc_usb30_sec_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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reg = <0x18d050 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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reg = <0x18d058 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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reg = <0x18d054 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
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compatible = "qcom,gdsc";
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reg = <0x18d06c 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
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compatible = "qcom,gdsc";
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reg = <0x17d05c 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
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compatible = "qcom,gdsc";
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reg = <0x18d060 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu2_gdsc: qcom,gdsc@17d0a0 {
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compatible = "qcom,gdsc";
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reg = <0x18d090 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu2_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu3_gdsc: qcom,gdsc@17d0a4 {
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compatible = "qcom,gdsc";
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reg = <0x18d0a4 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu3_gdsc";
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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/* GPU_CC GDSCs */
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gpu_cc_cx_gdsc_hw_ctrl: syscon@3d9953c {
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compatible = "syscon";
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reg = <0x3d9953c 0x4>;
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};
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gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
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compatible = "qcom,gdsc";
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reg = <0x3d99108 0x4>;
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regulator-name = "gpu_cc_cx_gdsc";
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hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,retain-regs;
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status = "disabled";
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};
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gpu_cc_gx_acd_reset: syscon@3d99358 {
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compatible = "syscon";
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reg = <0x3d99358 0x4>;
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};
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gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
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compatible = "syscon";
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reg = <0x3d9958c 0x4>;
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};
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gpu_cc_gx_sw_reset: syscon@3d99058 {
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compatible = "syscon";
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reg = <0x3d99058 0x4>;
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};
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gpu_cc_gx_domain_addr: syscon@3d99504 {
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compatible = "syscon";
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reg = <0x3d99504 0x4>;
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};
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gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
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compatible = "qcom,gdsc";
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reg = <0x3d9905c 0x4>;
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regulator-name = "gpu_cc_gx_gdsc";
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parent-supply = <&VDD_GX_MXC_VOTER_LEVEL>;
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domain-addr = <&gpu_cc_gx_domain_addr>;
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sw-reset = <&gpu_cc_gx_sw_reset>,
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<&gpu_cc_gx_acd_reset>,
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<&gpu_cc_gx_acd_iroot_reset>;
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qcom,skip-disable-before-sw-enable;
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qcom,reset-aon-logic;
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qcom,retain-regs;
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status = "disabled";
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};
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/* VIDEO_CC GDSCs */
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video_cc_mvs0_gdsc: qcom,gdsc@abf809c {
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compatible = "qcom,gdsc";
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reg = <0xabf809c 0x4>;
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regulator-name = "video_cc_mvs0_gdsc";
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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video_cc_mvs0c_gdsc: qcom,gdsc@abf804c {
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compatible = "qcom,gdsc";
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reg = <0xabf804c 0x4>;
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regulator-name = "video_cc_mvs0c_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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video_cc_mvs1_gdsc: qcom,gdsc@abf80c0 {
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compatible = "qcom,gdsc";
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reg = <0xabf80c0 0x4>;
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regulator-name = "video_cc_mvs1_gdsc";
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qcom,retain-regs;
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qcom,support-hw-trigger;
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status = "disabled";
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};
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video_cc_mvs1c_gdsc: qcom,gdsc@abf8074 {
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compatible = "qcom,gdsc";
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reg = <0xabf8074 0x4>;
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regulator-name = "video_cc_mvs1c_gdsc";
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qcom,retain-regs;
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status = "disabled";
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};
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};
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414
qcom/lemans.dtsi
414
qcom/lemans.dtsi
@@ -1,3 +1,9 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-lemans.h>
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#include <dt-bindings/clock/qcom,dispcc-lemans.h>
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#include <dt-bindings/clock/qcom,gcc-lemans.h>
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#include <dt-bindings/clock/qcom,gpucc-lemans.h>
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#include <dt-bindings/clock/qcom,videocc-lemans.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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@@ -32,6 +38,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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@@ -54,6 +61,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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@@ -70,6 +78,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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@@ -86,6 +95,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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@@ -102,6 +112,7 @@
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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@@ -124,6 +135,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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@@ -140,6 +152,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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@@ -156,6 +169,7 @@
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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cache-size = <0x20000>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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@@ -433,6 +447,14 @@
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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rpmhcc: qcom,rpmhcc {
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compatible = "qcom,lemans-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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status = "okay";
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};
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};
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};
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@@ -553,6 +575,398 @@
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_0_pipe_clk: pcie_0_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie_1_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
|
||||
clock-output-names = "pcie_1_pipe_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pcie_phy_aux_clk: pcie_phy_aux_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "pcie_phy_aux_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rxc0_ref_clk: rxc0_ref_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "rxc0_ref_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rxc1_ref_clk: rxc1_ref_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "rxc0_ref_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_card_rx_symbol_0_clk: ufs_card_rx_symbol_0_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_card_rx_symbol_0_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_card_rx_symbol_1_clk: ufs_card_rx_symbol_1_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_card_rx_symbol_1_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_card_tx_symbol_0_clk: ufs_card_tx_symbol_0_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_card_tx_symbol_0_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_phy_wrapper_gcc_usb30_sec_pipe_clk: usb3_phy_wrapper_gcc_usb30_sec_pipe_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000>;
|
||||
clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,lemans-gcc", "syscon";
|
||||
reg = <0x100000 0xc7018>;
|
||||
reg-name = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
|
||||
<&pcie_phy_aux_clk>, <&rxc0_ref_clk>, <&rxc1_ref_clk>, <&sleep_clk>,
|
||||
<&ufs_card_rx_symbol_0_clk>, <&ufs_card_rx_symbol_1_clk>,
|
||||
<&ufs_card_tx_symbol_0_clk>, <&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>;
|
||||
clock-names = "bi_tcxo", "pcie_0_pipe_clk", "pcie_1_pipe_clk",
|
||||
"pcie_phy_aux_clk", "rxc0_ref_clk", "rxc1_ref_clk", "sleep_clk",
|
||||
"ufs_card_rx_symbol_0_clk", "ufs_card_rx_symbol_1_clk",
|
||||
"ufs_card_tx_symbol_0_clk", "ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_prim_pipe_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,lemans-camcc", "syscon";
|
||||
reg = <0xade0000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_CAMERA_AHB_CLK>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "iface", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
dispcc0: clock-controller@af00000 {
|
||||
compatible = "qcom,lemans-dispcc0", "syscon";
|
||||
reg = <0xaf00000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
dispcc1: clock-controller@22100000 {
|
||||
compatible = "qcom,lemans-dispcc1", "syscon";
|
||||
reg = <0x22100000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>, <&gcc GCC_DISP1_AHB_CLK>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpucc: clock-controller@3d90000 {
|
||||
compatible = "qcom,lemans-gpucc", "syscon";
|
||||
reg = <0x3d90000 0xa000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo", "iface", "gpll0_out_main", "gpll0_out_main_div";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
videocc: clock-controller@abf0000 {
|
||||
compatible = "qcom,lemans-videocc", "syscon";
|
||||
reg = <0xabf0000 0x10000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "iface", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cpufreq_hw: qcom,cpufreq-hw@18591000 {
|
||||
compatible = "qcom,cpufreq-hw-epss";
|
||||
reg = <0x18591000 0x1000>, <0x18593000 0x1000>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
qcom,skip-enable-check;
|
||||
qcom,lut-row-size = <4>;
|
||||
#freq-domain-cells = <2>;
|
||||
};
|
||||
|
||||
qcom,cpufreq-hw-debug@18591000 {
|
||||
compatible = "qcom,cpufreq-hw-epss-debug";
|
||||
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
|
||||
};
|
||||
|
||||
apsscc: syscon@182a0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x182a0000 0x1c>;
|
||||
};
|
||||
|
||||
mccc: syscon@90ba000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x90ba000 0x54>;
|
||||
};
|
||||
|
||||
debugcc: debug-clock-controller@0 {
|
||||
compatible = "qcom,lemans-debugcc";
|
||||
qcom,gcc = <&gcc>;
|
||||
qcom,camcc = <&camcc>;
|
||||
qcom,dispcc0 = <&dispcc0>;
|
||||
qcom,dispcc1 = <&dispcc1>;
|
||||
qcom,gpucc = <&gpucc>;
|
||||
qcom,videocc = <&videocc>;
|
||||
qcom,apsscc = <&apsscc>;
|
||||
qcom,mccc = <&mccc>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo_clk_src";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "lemans-4pmic-regulators.dtsi"
|
||||
#include "lemans-gdsc.dtsi"
|
||||
|
||||
&cam_cc_titan_top_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp0_cc_mdss_core_gdsc {
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp0_cc_mdss_core_int2_gdsc {
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp1_cc_mdss_core_gdsc {
|
||||
clocks = <&gcc GCC_DISP1_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp1_cc_mdss_core_int2_gdsc {
|
||||
clocks = <&gcc GCC_DISP1_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_emac0_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_emac1_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_pcie_0_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_pcie_1_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_ufs_card_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_ufs_phy_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_usb20_prim_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_usb30_prim_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gcc_usb30_sec_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu2_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hlos1_vote_turing_mmu_tbu3_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu_cc_cx_gdsc {
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu_cc_gx_gdsc {
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_GX_MXC_VOTER_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0c_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs1_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs1c_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user