mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
632 lines
13 KiB
Plaintext
632 lines
13 KiB
Plaintext
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,scuba.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-scuba.h>
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#include <dt-bindings/clock/qcom,gpucc-scuba.h>
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#include <dt-bindings/clock/qcom,dispcc-scuba.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SCUBA_AUTO";
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compatible = "qcom,sa410m";
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qcom,msm-id = <441 0x10000>, <471 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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chosen: chosen { };
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mem-offline {
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compatible = "qcom,mem-offline";
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offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
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<0x1 0xc0000000 0x0 0x80000000>,
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<0x2 0xc0000000 0x1 0x40000000>;
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granule = <512>;
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};
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aliases { };
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firmware: firmware {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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soc: soc { };
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@45600000 {
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no-map;
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reg = <0x0 0x45600000 0x0 0x700000>;
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};
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xbl_aop_mem: xbl_aop_mem@45e00000 {
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no-map;
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reg = <0x0 0x45e00000 0x0 0x100000>;
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};
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sec_apps_mem: sec_apps_region@45fff000 {
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no-map;
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reg = <0x0 0x45fff000 0x0 0x1000>;
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};
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smem_region: smem@46000000 {
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no-map;
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reg = <0x0 0x46000000 0x0 0x200000>;
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};
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pil_modem_mem: modem_region@4ab00000 {
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no-map;
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reg = <0x0 0x4ab00000 0x0 0x6900000>;
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};
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wlan_msa_mem: wlan_msa_region@51400000 {
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no-map;
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reg = <0x0 0x51400000 0x0 0x100000>;
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};
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pil_adsp_mem: adsp_regions@51500000 {
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no-map;
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reg = <0x0 0x51500000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: ips_fw_region@52900000 {
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no-map;
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reg = <0x0 0x52900000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi_region@52910000 {
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no-map;
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reg = <0x0 0x52910000 0x0 0x5000>;
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};
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removed_region: removed_region@60000000 {
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no-map;
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reg = <0x0 0x60000000 0x0 0x3900000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x800000>;
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};
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secure_display_memory: secure_display_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x5c00000>;
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};
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cont_splash_memory: cont_splash_region@5c000000 {
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reg = <0x0 0x5c000000 0x0 0x00f00000>;
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label = "cont_splash_region";
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};
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dfps_data_memory: dfps_data_region@5cf00000 {
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reg = <0x0 0x5cf00000 0x0 0x0100000>;
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label = "dfps_data_region";
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};
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disp_rdump_memory: disp_rdump_region@5c000000 {
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reg = <0x0 0x5c000000 0x0 0x00f00000>;
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label = "disp_rdump_region";
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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memshare_mem: memshare_region {
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compatible = "shared-dma-pool";
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no-map;
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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alignment = <0x0 0x100000>;
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size = <0x0 0x800000>;
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};
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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smem_mem: smem@46000000 {
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no-map;
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reg = <0x0 0x46000000 0x0 0x200000>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0xf200000 0x10000>, /* GICD */
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<0xf300000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <0>;
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@f120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf120000 0x1000>;
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clock-frequency = <19200000>;
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frame@f121000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf121000 0x1000>,
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<0xf122000 0x1000>;
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};
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frame@f123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf123000 0x1000>;
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status = "disabled";
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};
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frame@f124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf124000 0x1000>;
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status = "disabled";
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};
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frame@f125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf125000 0x1000>;
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status = "disabled";
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};
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frame@f126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf126000 0x1000>;
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status = "disabled";
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};
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frame@f127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf127000 0x1000>;
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status = "disabled";
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};
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frame@f128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf128000 0x1000>;
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status = "disabled";
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};
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};
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rpm_msg_ram: memory@045f0000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x45f0000 0x7000>;
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};
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apcs_glb: mailbox@0f111000 {
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compatible = "qcom,scuba-apcs-hmss-global";
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reg = <0xF111000 0x1000>;
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#mbox-cells = <1>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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qcom,rpm_glink_ssr {
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qcom,glink-channels = "glink_ssr";
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// qcom,notify-edges = <&glink_adsp>;
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};
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "chip_sleep_clk";
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#clock-cells = <0>;
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};
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};
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-scuba";
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#clock-cells = <1>;
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};
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gcc: clock-controller@1400000 {
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compatible = "qcom,scuba-gcc", "syscon";
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reg = <0x1400000 0x1f0000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MX_LEVEL>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&sleep_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@5f00000 {
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compatible = "qcom,scuba-dispcc", "syscon";
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reg = <0x5f00000 0x20000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&sleep_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao",
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"gcc_disp_gpll0_div_clk_src",
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"sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@5990000 {
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compatible = "qcom,scuba-gpucc", "syscon";
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reg = <0x5990000 0x9000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
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clock-names = "bi_tcxo", "gpll0_out_main";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mccc_debug: syscon@447d200 {
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compatible = "syscon";
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reg = <0x447d200 0x100>;
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};
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cpucc_debug: syscon@f11101c {
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compatible = "syscon";
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reg = <0xf11101c 0x4>;
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};
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debugcc: clock-controller@0 {
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compatible = "qcom,scuba-debugcc";
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qcom,gcc = <&gcc>;
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qcom,dispcc = <&dispcc>;
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qcom,gpucc = <&gpucc>;
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qcom,mccc = <&mccc_debug>;
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qcom,cpucc = <&cpucc_debug>;
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clock-names = "xo_clk_src";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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#clock-cells = <1>;
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};
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cpufreq_hw: qcom,cpufreq-hw {
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compatible = "qcom,cpufreq-hw";
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reg = <0xf521000 0x1400>;
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reg-names = "freq-domain0";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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qcom,no-accumulative-counter;
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qcom,max-lut-entries = <12>;
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#freq-domain-cells = <1>;
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};
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clk_virt: interconnect@0 {
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compatible = "qcom,scuba-clk_virt";
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qcom,keepalive;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_QUP_CLK>,
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<&rpmcc RPM_SMD_QUP_A_CLK>;
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};
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system_noc: interconnect0@1880000 {
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reg = <0x1880000 0x5e080>;
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compatible = "qcom,scuba-sys_noc";
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qcom,keepalive;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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};
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mmnrt_virt: interconnect1@1880000 {
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reg = <0x1880000 0x5e080>;
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compatible = "qcom,scuba-mmnrt_virt";
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qcom,util-factor = <142>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
|
|
<&rpmcc RPM_SMD_MMNRT_A_CLK>;
|
|
};
|
|
|
|
mmrt_virt: interconnect2@1880000 {
|
|
reg = <0x1880000 0x5e080>;
|
|
compatible = "qcom,scuba-mmrt_virt";
|
|
qcom,util-factor = <139>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
|
|
<&rpmcc RPM_SMD_MMRT_A_CLK>;
|
|
};
|
|
|
|
config_noc: interconnect@1900000 {
|
|
reg = <0x01900000 0x9200>;
|
|
compatible = "qcom,scuba-config_noc";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
|
|
<&rpmcc RPM_SMD_CNOC_A_CLK>;
|
|
};
|
|
|
|
bimc: interconnect@4480000 {
|
|
reg = <0x4480000 0x80000>;
|
|
compatible = "qcom,scuba-bimc";
|
|
qcom,util-factor = <153>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
|
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
qcom_scm: qcomscm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
|
|
};
|
|
|
|
#include "pm2250-rpm-regulator.dtsi"
|
|
#include "scuba-regulator.dtsi"
|
|
#include "monaco-gdsc.dtsi"
|
|
|
|
&gcc_camss_top_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_vcodec0_gdsc {
|
|
reg = <0x1458098 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_venus_gdsc {
|
|
reg = <0x145807c 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
|
|
qcom,gds-timeout = <500>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
|
|
qcom,gds-timeout = <500>;
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_sw_reset {
|
|
reg = <0x5991008 0x4>;
|
|
};
|
|
|
|
&gpu_cx_hw_ctrl {
|
|
reg = <0x5991540 0x4>;
|
|
};
|
|
|
|
&gpu_gx_domain_addr {
|
|
reg = <0x5991508 0x4>;
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
reg = <0x599106c 0x4>;
|
|
/delete-property/ qcom,gds-timeout;
|
|
/delete-property/ qcom,clk-dis-wait-val;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
reg = <0x599100c 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
#include "msm-arm-smmu-scuba_auto.dtsi"
|