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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add smmu dt nodes for scuba_auto
Add smmu dt nodes for scuba_auto Change-Id: Ieb3f7e19a2478dc0f0bf861ab7fe6f5392c0abd7
This commit is contained in:
Akshay Adiga
158
qcom/msm-arm-smmu-scuba_auto.dtsi
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158
qcom/msm-arm-smmu-scuba_auto.dtsi
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@@ -0,0 +1,158 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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apps_smmu: apps-smmu@0xc600000 {
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status = "okay";
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compatible = "qcom,qsmmu-v500";
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reg = <0xc600000 0x80000>,
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<0xc782000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,actlr =
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/* For rt TBU +3 deep PF */
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<0x400 0x3ff 0x103>,
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/* For nrt TBU +3 deep PF */
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<0x800 0x3ff 0x103>;
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anoc_1_tbu: anoc_1_tbu@0xc785000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc785000 0x1000>,
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<0xc782200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interconnects = <&bimc MASTER_AMPSS_M0
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&config_noc SLAVE_IMEM_CFG>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,iova-width = <36>;
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};
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mm_rt_tbu: mm_rt_tbu@0xc789000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc789000 0x1000>,
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<0xc782208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&mmrt_virt MASTER_MDP_PORT0
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&bimc SLAVE_EBI_CH0>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc78d000 0x1000>,
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<0xc782210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&mmnrt_virt MASTER_CAMNOC_SF
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&bimc SLAVE_EBI_CH0>,
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<&bimc MASTER_AMPSS_M0
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&system_noc SLAVE_TCU>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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};
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dma_dev@0x0 {
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compatible = "qcom,iommu-dma";
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memory-region = <&system_cma>;
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};
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iommu_test_device {
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compatible = "qcom,iommu-debug-test";
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apps_iommu_test_device {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x1E0 0>;
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};
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apps_iommu_coherent_test_device {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x1E1 0>;
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dma-coherent;
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};
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};
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};
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@@ -547,6 +547,15 @@
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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qcom-secure-buffer {
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compatible = "qcom,secure-buffer";
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};
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qcom_scm: qcomscm {
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compatible = "qcom,scm";
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};
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};
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#include "pm2250-rpm-regulator.dtsi"
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@@ -618,3 +627,5 @@
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reg = <0x599100c 0x4>;
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status = "ok";
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};
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#include "msm-arm-smmu-scuba_auto.dtsi"
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