Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add NFC device node for Palima

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Device node changes required on Palima,
describing the GPIO configuration for
Nfc controller chip.

Modified corresponding Nfc device node
for ATP, CDP, MTP & QRD platforms.

Change-Id: I707a2fa66c4a3896375f92f315f3eab07a1b7744
This commit is contained in:
Khageswararao Rao B
2021-11-29 12:25:49 +05:30
parent 3c77e2202f
commit 00f7554e47
5 changed files with 155 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
qcom/cape-atp.dtsi
View File

@@ -74,3 +74,27 @@
pinctrl-2 = <&ts_release>;
};
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};

24
qcom/cape-cdp.dtsi
View File

@@ -86,6 +86,30 @@
status = "ok";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_spi {
status = "ok";

24
qcom/cape-mtp.dtsi
View File

@@ -90,6 +90,30 @@
qcom,wireless-fw-name = "idt9415.bin";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_spi {
status = "ok";

59
qcom/cape-pinctrl.dtsi
View File

@@ -2487,6 +2487,65 @@
};
};
nfc {
nfc_int_active: nfc_int_active {
/* active state */
mux {
/* NFC Read Interrupt */
pins = "gpio46";
function = "gpio";
};
config {
pins = "gpio46";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_int_suspend: nfc_int_suspend {
/* sleep state */
mux {
/* NFC Read Interrupt */
pins = "gpio46";
function = "gpio";
};
config {
pins = "gpio46";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_enable_active: nfc_enable_active {
mux {
/* Enable, Firmware and Clock request gpios */
pins = "gpio34", "gpio45", "gpio35";
function = "gpio";
};
config {
pins = "gpio34", "gpio45", "gpio35";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_enable_suspend: nfc_enable_suspend {
mux {
pins = "gpio34", "gpio45", "gpio35";
function = "gpio";
};
config {
pins = "gpio34", "gpio45", "gpio35";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
};
/* touchscreen pins */
pmx_ts_active {
ts_active: ts_active {

24
qcom/cape-qrd.dtsi
View File

@@ -135,6 +135,30 @@
qcom,wireless-fw-name = "idt9415.bin";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_spi {
status = "ok";