Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: Add GPU frequencies with ACD DVM values for neo"

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qctecmdr
2023-05-12 00:21:16 -07:00
committed by Gerrit - the friendly Code Review server
parent bb861bbb17 3b0edfe4e0
commit 015bc0a9f5
1 changed files with 141 additions and 10 deletions
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151
qcom/neo-gpu.dtsi
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@@ -41,7 +41,6 @@
qcom,ubwc-mode = <3>;
qcom,no-nap;
qcom,initial-pwrlevel = <0>;
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
@@ -68,20 +67,152 @@
memory-region = <&gpu_microcode_mem>;
};
qcom,gpu-pwrlevels {
/*
* Speed-bin zero is default speed bin.
* For rest of the speed bins, speed-bin value
* is calculated as FMAX/4.8 MHz round up to zero
* decimal places plus two margin to account for
* clock jitters.
*/
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
compatible = "qcom,gpu-pwrlevel-bins";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <320000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <5>;
/* TURBO_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <843000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
qcom,acd-level = <0xA82E5FFD>;
};
/* TURBO */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <780000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <11>;
qcom,acd-level = <0xC0285FFD>;
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <11>;
qcom,acd-level = <0xC0285FFD>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <570000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <0xC0285FFD>;
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <450000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <0xC0285FFD>;
};
/* LOW SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <320000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <137>;
qcom,initial-pwrlevel = <3>;
/* NOM */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <644000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <11>;
qcom,bus-min = <8>;
qcom,bus-max = <11>;
qcom,acd-level = <0xC0285FFD>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <570000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <0xC0285FFD>;
};
/* SVS */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <450000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <0xC0285FFD>;
};
/* LOW SVS */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <320000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
};
};
};
};