ARM: dts: msm: Add QUPv3 console node

Enable console support on waipio.

Change-Id: I7aaba969dbffa92541e07ca70be8a91a492cea7f

qcom/waipio-pinctrl.dtsi

@@ -1,3 +1,30 @@
 &tlmm {
+	qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
+		qupv3_se7_2uart_active: qupv3_se7_2uart_active {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
 };
 

qcom/waipio-qupv3.dtsi

@@ -0,0 +1,26 @@
+&soc {
+
+	/* QUPv3_0  wrapper  instance : North QUP*/
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		status = "ok";
+	};
+
+	/* PORed Debug UART */
+	qupv3_se7_2uart: qcom,qup_uart@99c000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x99c000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se7_2uart_active>;
+		pinctrl-1 = <&qupv3_se7_2uart_sleep>;
+		interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "ok";
+	};
+};

qcom/waipio.dtsi

@@ -21,7 +21,9 @@
 
 	chosen: chosen { };
 
-	aliases { };
+	aliases {
+		serial0 = &qupv3_se7_2uart;
+	 };
 
 	cpus {
 		#address-cells = <2>;
@@ -293,5 +295,8 @@
 		#reset-cells = <1>;
 	};
 };
+
+
+#include "waipio-qupv3.dtsi"
 #include "waipio-pinctrl.dtsi"
 #include "waipio-regulators.dtsi"