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ARM: dts: msm: Add initial base changes for neo

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Add initial changes to support neo platform.

Change-Id: I906f550afbd7307faf30b8e5ca6f487d1d6f83e0
This commit is contained in:
Mayank Grover
2021-08-10 12:18:13 +05:30
committed by Amrit Anand
parent ae3149a7d4
commit 0b103bbfa5
5 changed files with 226 additions and 7 deletions
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6
qcom/neo-rumi-overlay.dts
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@@ -4,8 +4,8 @@
#include "neo-rumi.dtsi"
/ {
/** DUMMY DEVICE TREE - Place holder only **/
model = "Qualcomm Technologies, Inc. NEO RUMI DUMMY DT";
model = "Qualcomm Technologies, Inc. NEO RUMI";
compatible = "qcom,neo-rumi", "qcom,neo", "qcom,rumi";
qcom,msm-id = <525 0x10000>;
qcom,board-id = <0x1000F 0>;
};

4
qcom/neo-rumi.dts
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@@ -4,7 +4,7 @@
#include "neo-rumi.dtsi"
/ {
/** DUMMY DEVICE TREE - Place holder only **/
model = "Qualcomm Technologies, Inc. NEO RUMI DUMMY DT";
model = "Qualcomm Technologies, Inc. NEO RUMI";
compatible = "qcom,neo-rumi", "qcom,neo", "qcom,rumi";
qcom,board-id = <0x1000f 0>;
};

12
qcom/neo-rumi.dtsi
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@@ -1 +1,13 @@
&soc {
timer {
clock-frequency = <5000000>;
};
timer@17420000 {
clock-frequency = <5000000>;
};
qcom,wdt@17410000 {
status = "disabled";
};
};

4
qcom/neo.dts
View File

@@ -3,7 +3,7 @@
#include "neo.dtsi"
/ {
/** DUMMY DEVICE TREE - Place holder only **/
model = "Qualcomm Technologies, Inc. NEO SoC DUMMY DT";
model = "Qualcomm Technologies, Inc. NEO SoC";
compatible = "qcom,neo";
qcom,board-id = <0 0>;
};

207
qcom/neo.dtsi
View File

@@ -1,2 +1,209 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Qualcomm Technologies, Inc. NEO";
compatible = "qcom,neo";
qcom,msm-id = <525 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_2>;
L3_2: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_3>;
L3_3: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
soc: soc { };
chosen { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@0x17200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17200000 0x10000>, /* GICD */
<0x17260000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdog: qcom,wdt@17410000 {
compatible = "qcom,msm-watchdog";
reg = <0x17410000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17420000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17420000 0x1000>;
clock-frequency = <19200000>;
frame@17421000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17421000 0x1000>,
<0x17422000 0x1000>;
};
frame@17423000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17423000 0x1000>;
status = "disabled";
};
frame@17425000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17425000 0x1000>;
status = "disabled";
};
frame@17427000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17427000 0x1000>;
status = "disabled";
};
frame@17429000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17429000 0x1000>;
status = "disabled";
};
frame@1742b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1742b000 0x1000>;
status = "disabled";
};
frame@1742d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1742d000 0x1000>;
status = "disabled";
};
};
};