mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: add initial PCIe nodes for lahaina
Add initial devicetree nodes to support PCIe0 and PCIe1 on Lahaina. Change-Id: If0e811a6436ae99018d01a34d131bb06038c80a9
This commit is contained in:
Tony Truong
296
qcom/lahaina-pcie.dtsi
Normal file
296
qcom/lahaina-pcie.dtsi
Normal file
@@ -0,0 +1,296 @@
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#include <dt-bindings/clock/qcom,gcc-lahaina.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 94 0>;
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wake-gpio = <&tlmm 96 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p8-supply = <&pm8350_l6>;
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vreg-0p9-supply = <&pm8350_l5>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 97200>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale =
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<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
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RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
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interconnect-names = "icc_path";
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interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_0_AUX_CLK>,
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<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_CLKREF_EN>,
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<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,
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<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&clock_gcc GCC_PCIE_0_BCR>,
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<&clock_gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1c00>;
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iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
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<0x100 &apps_smmu 0x1c01 0x1>;
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qcom,boot-option = <0x1>;
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qcom,drv-supported;
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qcom,drv-l1ss-timeout-us = <10000>;
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qcom,use-19p2mhz-aux-clk;
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qcom,no-l0s-supported;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <70>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,pcie-phy-ver = <0>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0 0 0>;
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status = "disabled";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a10040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a10040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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};
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pcie1: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c08000 0x3000>,
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<0x01c0e000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <1>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie1>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie1_msi>;
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perst-gpio = <&tlmm 97 0>;
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wake-gpio = <&tlmm 99 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_perst_default
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&pcie1_clkreq_default
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&pcie1_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
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vreg-1p8-supply = <&pm8350_l6>;
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vreg-0p9-supply = <&pm8350_l5>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 97200>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale =
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<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
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RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
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interconnect-names = "icc_path";
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interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_1_AUX_CLK>,
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<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_1_CLKREF_EN>,
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<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,
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<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
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clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
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"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
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"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
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"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>;
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resets = <&clock_gcc GCC_PCIE_1_BCR>,
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<&clock_gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "pcie_1_core_reset",
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"pcie_1_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1c80>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>;
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qcom,boot-option = <0x1>;
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qcom,drv-supported;
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qcom,use-19p2mhz-aux-clk;
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qcom,no-l0s-supported;
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qcom,slv-addr-space-size = <0x20000000>;
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qcom,ep-latency = <10>;
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qcom,pcie-phy-ver = <0>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0 0 0>;
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status = "disabled";
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pcie1_rp: pcie1_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie1_msi: qcom,pcie1_msi@17a10040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a10040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@@ -1342,6 +1342,88 @@
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};
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};
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};
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pcie0 {
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pcie0_perst_default: pcie0_perst_default {
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mux {
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pins = "gpio94";
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function = "gpio";
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};
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config {
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pins = "gpio94";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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pins = "gpio95";
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function = "pci_e0";
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};
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config {
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pins = "gpio95";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_wake_default: pcie0_wake_default {
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mux {
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pins = "gpio96";
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function = "gpio";
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};
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config {
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pins = "gpio96";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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pcie1 {
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pcie1_perst_default: pcie1_perst_default {
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mux {
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pins = "gpio97";
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function = "gpio";
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};
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config {
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pins = "gpio97";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie1_clkreq_default: pcie1_clkreq_default {
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mux {
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pins = "gpio98";
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function = "pci_e1";
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};
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config {
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pins = "gpio98";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie1_wake_default: pcie1_wake_default {
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mux {
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pins = "gpio99";
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function = "gpio";
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};
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config {
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pins = "gpio99";
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drive-strength = <2>;
|
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bias-pull-up;
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||||
};
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||||
};
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||||
};
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||||
};
|
||||
|
||||
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
|
||||
|
||||
@@ -34,6 +34,8 @@
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||||
aliases {
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
|
||||
serial0 = &qupv3_se3_2uart;
|
||||
pci-domain0 = &pcie0; /* PCIe0 domain */
|
||||
pci-domain1 = &pcie1; /* PCIe1 domain */
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -2210,3 +2212,4 @@
|
||||
#include "lahaina-qupv3.dtsi"
|
||||
#include "lahaina-vidc.dtsi"
|
||||
#include "lahaina-cvp.dtsi"
|
||||
#include "lahaina-pcie.dtsi"
|
||||
|
||||
Reference in New Issue
Block a user