Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: add spi, i2c, gpi nodes for Parrot SVM"

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qctecmdr
2022-05-20 17:23:25 -07:00
committed by Gerrit - the friendly Code Review server
parent f09a5720fa 3718561cb3
commit 1c0a00f68a
2 changed files with 79 additions and 5 deletions
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11
qcom/parrot-qupv3.dtsi
View File

@@ -332,7 +332,8 @@
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x3f>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x3e>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
dma-coherent;
@@ -500,8 +501,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dmas = <&gpi_dma1 0 3 3 64 2>,
<&gpi_dma1 1 3 3 64 2>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
@@ -522,8 +523,8 @@
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dmas = <&gpi_dma1 0 3 1 64 2>,
<&gpi_dma1 1 3 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;

73
qcom/parrot-vm.dtsi
View File

@@ -19,6 +19,8 @@
};
qcom,vm-config {
iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0>;
gic-irq-ranges = <325 325>; /* PVM->SVM IRQ transfer */
vdevices {
gvsock-message-queue-pair {
status = "disabled";
@@ -74,4 +76,75 @@
/delete-node/ i2c@990000;
/delete-node/ spi@990000;
qup_iommu_group: qup_common_iommu_group {
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0xac0000 0x2000>;
iommus = <&apps_smmu 0x418 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
status = "ok";
};
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x418 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,gpii-mask = <0x40>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* TUI over I2C */
qupv3_se9_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_1>;
qcom,le-vm;
status = "disabled";
};
qupv3_se9_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
qcom,le-vm;
status = "disabled";
};
};