mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
ARM: dts: msm: Add QUPV3 SE dtsi entries for ravelin
Added dt node entries of UART, I2C, SPI, GSI for ravelin. Change-Id: I839e36e95f35a8248f72ffb9a7449f3d6ff39133
This commit is contained in:
Yatish Kumar Singh
@@ -9,8 +9,8 @@
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {
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qupv3_se2_2uart_tx_active: qupv3_se2_2uart_tx_active {
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qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
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qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active {
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mux {
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pins = "gpio22";
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function = "qup1_se2_l2";
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@@ -23,7 +23,7 @@
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};
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};
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qupv3_se2_2uart_rx_active: qupv3_se2_2uart_rx_active {
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qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active {
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mux {
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pins = "gpio23";
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function = "qup1_se2_l3";
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@@ -36,7 +36,7 @@
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};
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};
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qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {
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qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
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mux {
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pins = "gpio22", "gpio23";
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function = "gpio";
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@@ -50,6 +50,964 @@
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};
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};
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qupv3_se2_4uart_pins: qupv3_se2_4uart_pins {
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qupv3_se2_default_cts: qupv3_se2_default_cts {
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mux {
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pins = "gpio14";
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function = "gpio";
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};
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config {
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pins = "gpio14";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se2_default_rts: qupv3_se2_default_rts {
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mux {
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pins = "gpio15";
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function = "gpio";
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};
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config {
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pins = "gpio15";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se2_default_tx: qupv3_se2_default_tx {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_default_rx: qupv3_se2_default_rx {
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mux {
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pins = "gpio17";
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function = "gpio";
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};
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config {
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pins = "gpio17";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se2_cts: qupv3_se2_cts {
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mux {
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pins = "gpio14";
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function = "qup0_se2_l0";
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};
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config {
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pins = "gpio14";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se2_rts: qupv3_se2_rts {
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mux {
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pins = "gpio15";
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function = "qup0_se2_l1";
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};
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config {
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pins = "gpio15";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se2_tx: qupv3_se2_tx {
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mux {
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pins = "gpio16";
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function = "qup0_se2_l2";
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};
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config {
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pins = "gpio16";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_rx: qupv3_se2_rx {
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mux {
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pins = "gpio17";
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function = "qup0_se2_l3";
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};
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config {
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pins = "gpio17";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se0_2uart_pins: qupv3_se0_2uart_pins {
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qupv3_se0_2uart_tx_active: qupv3_se0_2uart_tx_active {
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mux {
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pins = "gpio34";
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function = "qup0_se0_l2";
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};
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config {
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pins = "gpio34";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se0_2uart_rx_active: qupv3_se0_2uart_rx_active {
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mux {
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pins = "gpio35";
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function = "qup0_se0_l3";
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};
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config {
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pins = "gpio35";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep {
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mux {
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pins = "gpio34", "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio34", "gpio35";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
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mux {
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pins = "gpio4";
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function = "qup0_se0_l0";
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};
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config {
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pins = "gpio4";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
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mux {
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pins = "gpio5";
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function = "qup0_se0_l1";
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};
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config {
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pins = "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio4", "gpio5";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
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mux {
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pins = "gpio10";
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function = "qup0_se1_l0";
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};
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config {
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pins = "gpio10";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
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mux {
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pins = "gpio11";
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function = "qup0_se1_l1";
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};
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config {
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pins = "gpio11";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio10", "gpio11";
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function = "gpio";
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};
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config {
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pins = "gpio10", "gpio11";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
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mux {
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pins = "gpio10";
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function = "qup0_se1_l0";
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};
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config {
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pins = "gpio10";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
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mux {
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pins = "gpio11";
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function = "qup0_se1_l1";
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};
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config {
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pins = "gpio11";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
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mux {
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pins = "gpio12";
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function = "qup0_se1_l2";
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};
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config {
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pins = "gpio12";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
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mux {
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pins = "gpio13";
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function = "qup0_se1_l3";
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};
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config {
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pins = "gpio13";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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function = "gpio";
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};
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config {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
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qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
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mux {
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pins = "gpio18";
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function = "qup0_se3_l0";
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};
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config {
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pins = "gpio18";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
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mux {
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pins = "gpio19";
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function = "qup0_se3_l1";
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};
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config {
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pins = "gpio19";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
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mux {
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pins = "gpio18", "gpio19";
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function = "gpio";
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};
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config {
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pins = "gpio18", "gpio19";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se3_spi_pins: qupv3_se3_spi_pins {
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qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active {
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mux {
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pins = "gpio18";
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function = "qup0_se3_l0";
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};
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config {
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pins = "gpio18";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active {
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mux {
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pins = "gpio19";
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function = "qup0_se3_l1";
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};
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config {
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pins = "gpio19";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active {
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mux {
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pins = "gpio20";
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function = "qup0_se3_l2";
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};
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config {
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pins = "gpio20";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active {
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mux {
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pins = "gpio21";
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function = "qup0_se3_l3";
|
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};
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config {
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pins = "gpio21";
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drive-strength = <6>;
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bias-pull-down;
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};
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};
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qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
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mux {
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pins = "gpio18", "gpio19",
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"gpio20", "gpio21";
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function = "gpio";
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};
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config {
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pins = "gpio18", "gpio19",
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"gpio20", "gpio21";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
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qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
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mux {
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pins = "gpio8";
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function = "qup0_se4_l0_mira";
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};
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config {
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pins = "gpio8";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
|
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mux {
|
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pins = "gpio9";
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function = "qup0_se4_l1_mira";
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};
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config {
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pins = "gpio9";
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drive-strength = <2>;
|
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bias-pull-up;
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};
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};
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qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
|
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mux {
|
||||
pins = "gpio8", "gpio9";
|
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function = "gpio";
|
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};
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|
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config {
|
||||
pins = "gpio8", "gpio9";
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drive-strength = <2>;
|
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bias-disable;
|
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};
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};
|
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};
|
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qupv3_se4_spi_pins: qupv3_se4_spi_pins {
|
||||
qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio8";
|
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function = "qup0_se4_l0_mira";
|
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};
|
||||
|
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config {
|
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pins = "gpio8";
|
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drive-strength = <6>;
|
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bias-pull-down;
|
||||
};
|
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};
|
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|
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qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio9";
|
||||
function = "qup0_se4_l1_mira";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio9";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
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qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio6";
|
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function = "qup0_se4_l2";
|
||||
};
|
||||
|
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config {
|
||||
pins = "gpio6";
|
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drive-strength = <6>;
|
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bias-pull-down;
|
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};
|
||||
};
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qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio7";
|
||||
function = "qup0_se4_l3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio7";
|
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drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
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|
||||
qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9",
|
||||
"gpio6", "gpio7";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio8", "gpio9",
|
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"gpio6", "gpio7";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
|
||||
qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio0";
|
||||
function = "qup1_se0_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio1";
|
||||
function = "qup1_se0_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_pins: qupv3_se5_spi_pins {
|
||||
qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio0";
|
||||
function = "qup1_se0_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio1";
|
||||
function = "qup1_se0_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio1";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio2";
|
||||
function = "qup1_se0_l2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio2";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio3";
|
||||
function = "qup1_se0_l3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio3";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1",
|
||||
"gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1",
|
||||
"gpio2", "gpio3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
|
||||
qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio50";
|
||||
function = "qup1_se1_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio50";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio51";
|
||||
function = "qup1_se1_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio51";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio50", "gpio51";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio50", "gpio51";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_pins: qupv3_se6_spi_pins {
|
||||
qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio50";
|
||||
function = "qup1_se1_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio50";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio51";
|
||||
function = "qup1_se1_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio51";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio26";
|
||||
function = "qup1_se1_l2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio27";
|
||||
function = "qup1_se1_l3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio27";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio50", "gpio51",
|
||||
"gpio26", "gpio27";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio50", "gpio51",
|
||||
"gpio26", "gpio27";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
|
||||
qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio24";
|
||||
function = "qup1_se3_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "qup1_se3_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio25";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_pins: qupv3_se8_spi_pins {
|
||||
qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio24";
|
||||
function = "qup1_se3_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "qup1_se3_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio25";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio51";
|
||||
function = "qup1_se3_l2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio51";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio50";
|
||||
function = "qup1_se3_l3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio50";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio51", "gpio50";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio51", "gpio50";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
|
||||
qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio91";
|
||||
function = "qup1_se4_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio91";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio90";
|
||||
function = "qup1_se4_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio90";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio91", "gpio90";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio91", "gpio90";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_pins: qupv3_se9_spi_pins {
|
||||
qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio91";
|
||||
function = "qup1_se4_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio91";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio90";
|
||||
function = "qup1_se4_l1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio90";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio48";
|
||||
function = "qup1_se4_l2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio48";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio43";
|
||||
function = "qup1_se4_l3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio91", "gpio90",
|
||||
"gpio48", "gpio43";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio91", "gpio90",
|
||||
"gpio48", "gpio43";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* WSA speaker reset pins */
|
||||
spkr_1_sd_n {
|
||||
spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
|
||||
|
||||
@@ -1,37 +1,487 @@
|
||||
&soc {
|
||||
/* QUPv3_1 wrapper instance */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0xac0000 0x2000>;
|
||||
/*
|
||||
* qcom,msm-bus,num-paths = <3>;
|
||||
* interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
* interconnects =
|
||||
* <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
* <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
* <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
* iommus = <&apps_smmu 0x43 0x0>;
|
||||
* qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
* qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
* qcom,iommu-dma = "fastmap";
|
||||
* dma-coherent;
|
||||
*/
|
||||
/* QUPv3 SE Instances
|
||||
* Qup0 0: SE 0
|
||||
* Qup0 1: SE 1
|
||||
* Qup0 2: SE 2
|
||||
* Qup0 3: SE 3
|
||||
* Qup0 4: SE 4
|
||||
* Qup1 0: SE 5
|
||||
* Qup1 1: SE 6
|
||||
* Qup1 2: SE 7
|
||||
* Qup1 3: SE 8
|
||||
* Qup1 4: SE 9
|
||||
*/
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma0: qcom,gpi-dma@900000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x900000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x176 0x0>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,static-gpii-mask = <0x1>;
|
||||
qcom,gpii-mask = <0x3e>;
|
||||
qcom,ev-factor = <2>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
dma-coherent;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* Debug UART Instance */
|
||||
qupv3_se2_2uart: qcom,qup_uart@a88000 {
|
||||
/* QUPv3_0 wrapper instance */
|
||||
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0x9c0000 0x2000>;
|
||||
qcom,msm-bus,num-paths = <3>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x163 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se2_4uart: qcom,qup_uart@988000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x988000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
|
||||
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
|
||||
pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
|
||||
<&qupv3_se2_tx>, <&qupv3_se2_rx>;
|
||||
pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
|
||||
<&qupv3_se2_tx>, <&qupv3_se2_default_rx>;
|
||||
pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
|
||||
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HST Debug UART Instance */
|
||||
qupv3_se0_2uart: qcom,qup_uart@980000 {
|
||||
compatible = "qcom,msm-geni-console";
|
||||
reg = <0x980000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se0_2uart_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_i2c: i2c@980000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x980000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 3 64 0>,
|
||||
<&gpi_dma0 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@984000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x984000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 3 64 0>,
|
||||
<&gpi_dma0 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@984000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x984000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
|
||||
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 1 64 0>,
|
||||
<&gpi_dma0 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_i2c: i2c@98c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x98c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 3 64 0>,
|
||||
<&gpi_dma0 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_spi: spi@98c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x98c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
|
||||
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se3_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 1 64 0>,
|
||||
<&gpi_dma0 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_i2c: i2c@990000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x990000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 3 64 0>,
|
||||
<&gpi_dma0 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_spi: spi@990000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x990000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
|
||||
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 1 64 0>,
|
||||
<&gpi_dma0 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma1: qcom,gpi-dma@a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0xa00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x416 0x0>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x3f>;
|
||||
qcom,ev-factor = <2>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
dma-coherent;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_1 wrapper instance */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0xac0000 0x2000>;
|
||||
qcom,msm-bus,num-paths = <3>;
|
||||
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
|
||||
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x403 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* PORed Debug UART Instance */
|
||||
qupv3_se7_2uart: qcom,qup_uart@a88000 {
|
||||
compatible = "qcom,msm-geni-console";
|
||||
reg = <0xa88000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_2uart_tx_active>, <&qupv3_se2_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se2_2uart_sleep>;
|
||||
pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se7_2uart_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||||
<&gpi_dma1 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
|
||||
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 1 64 0>,
|
||||
<&gpi_dma1 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_i2c: i2c@a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 3 64 0>,
|
||||
<&gpi_dma1 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
|
||||
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||||
<&gpi_dma1 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||||
<&gpi_dma1 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
qcom,shared;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_spi: spi@a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
|
||||
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 1 64 0>,
|
||||
<&gpi_dma1 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||||
<&gpi_dma1 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
|
||||
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||||
<&gpi_dma1 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -87,7 +87,7 @@
|
||||
|
||||
};
|
||||
|
||||
&qupv3_se2_2uart {
|
||||
&qupv3_se7_2uart {
|
||||
qcom,rumi_platform;
|
||||
};
|
||||
|
||||
|
||||
@@ -41,7 +41,9 @@
|
||||
};
|
||||
|
||||
aliases: aliases {
|
||||
serial0 = &qupv3_se2_2uart;
|
||||
serial0 = &qupv3_se7_2uart; /* Debug UART */
|
||||
serial1 = &qupv3_se0_2uart; /* HST debug UART */
|
||||
hsuart0 = &qupv3_se2_4uart;
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
|
||||
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
|
||||
mmc1 = &sdhc_2; /* SDC2 SD card slot */
|
||||
@@ -1853,7 +1855,7 @@
|
||||
#include "ipcc-test-ravelin.dtsi"
|
||||
#include "ravelin-qupv3.dtsi"
|
||||
|
||||
&qupv3_se2_2uart {
|
||||
&qupv3_se7_2uart {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user