mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: smmu enablement for parrot"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
commit
267a5cbb77
@@ -11,13 +11,29 @@
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qcom,use-3-lvl-tables;
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qcom,num-context-banks-override = <0x6>;
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qcom,num-smr-override = <0x6>;
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status = "disabled";
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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dma-coherent;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cc_cx_gdsc>;
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>;
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clock-names =
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"gpu_cc_cx_gmu",
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"gpu_cc_hub_cx_int",
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"gpu_cc_hlos1_vote_gpu_smmu",
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"gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb";
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qcom,actlr =
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/* All CBs of GFX: +15 deep PF */
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<0x000 0x7ff 0x32B>;
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@@ -179,14 +195,21 @@
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<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>;
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qcom,actlr =
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/* For display, camera +0 deep PF */
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<0x800 0x7ff 0x001>,
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<0x2800 0x7ff 0x001>,
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/* Display and camera clients, +0 PF */
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<0x800 0x3ff 0x1>,
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<0xc00 0x3ff 0x1>,
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<0x2000 0xE0 0x1>,
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<0x2100 0x60 0x1>,
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/* For video clients, +3 PF */
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<0x2180 0x27 0x103>,
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/* NSP clients, +15PF */
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<0x1000 0x3ff 0x303>,
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<0x1400 0x3ff 0x303>;
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/* For video +3 deep PF */
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<0x2180 0x42f 0x103>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&cnoc3 SLAVE_TCU>;
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qcom,active-only;
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anoc_1_tbu: anoc_1_tbu@151dd000 {
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compatible = "qcom,qsmmuv500-tbu";
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@@ -195,6 +218,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,micro-idle;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&cnoc3 SLAVE_IMEM>;
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qcom,active-only;
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};
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anoc_2_tbu: anoc_2_tbu@151e1000 {
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@@ -204,6 +230,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,micro-idle;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&cnoc3 SLAVE_IMEM>;
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qcom,active-only;
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};
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mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 {
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@@ -213,6 +242,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_HF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 {
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@@ -222,6 +256,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_HF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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compute_1_tbu: compute_1_tbu@151ed000 {
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@@ -231,6 +270,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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compute_0_tbu: compute_0_tbu@151f1000 {
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@@ -240,6 +284,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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lpass_tbu: lpass_tbu@151f5000 {
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@@ -249,6 +298,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1800 0x400>;
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qcom,micro-idle;
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interconnects = <&lpass_ag_noc MASTER_LPASS_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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pcie_tbu: pcie_tbu@151f9000 {
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@@ -258,6 +310,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1c00 0x400>;
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qcom,micro-idle;
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interconnects = <&pcie_noc MASTER_PCIE_0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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sf_0_tbu: sf_0_tbu@151fd000 {
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@@ -267,6 +322,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2000 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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};
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};
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@@ -301,9 +361,22 @@
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dma-coherent;
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};
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usecase4_kgsl {
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usecase4_apps_secure {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&apps_smmu 0x7e0 0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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};
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usecase5_kgsl {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&kgsl_smmu 0x7 0x400>;
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};
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usecase6_kgsl_dma {
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compatible = "qcom,iommu-debug-usecase";
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iommus = <&kgsl_smmu 0x407 0x400>;
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dma-coherent;
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};
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};
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};
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