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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
ARM: dts: msm: Add initial device tree for Cape
Add following initial nodes to support Cape
1. CPU Cluster Map
2. Interrupt Controller
3. Arch Timer & Mem Timer
Enable MTP,CDP,ATP devices for Cape
No Rumi Device Trees for Cape.
Change-Id: I8b15baa0a5da3630130c6fa7df9f523f586e43ba
This commit is contained in:
Auditya Bhattaram
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
aa3ee2274e
commit
28a74ad098
@@ -92,6 +92,9 @@ SoCs:
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- DIWALI
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compatible = "qcom,diwali"
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- CAPE
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compatible = "qcom,cape"
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- NEO
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compatible = "qcom,neo"
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@@ -257,5 +260,8 @@ compatible = "qcom,waipiop-hdk"
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compatible = "qcom,waipiop-mtp"
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compatible = "qcom,waipiop-cdp"
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compatible = "qcom,waipiop-qrd"
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compatible = "qcom,cape-mtp"
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compatible = "qcom,cape-atp"
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compatible = "qcom,cape-cdp"
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compatible = "qcom,diwali-rumi"
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compatible = "qcom,neo-rumi"
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@@ -166,6 +166,20 @@ else
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dtb-$(CONFIG_ARCH_DIWALI) += diwali-rumi.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_CAPE) += cape-mtp-overlay.dtbo \
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cape-cdp-overlay.dtbo \
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cape-atp-overlay.dtbo
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cape-mtp-overlay.dtbo-base := cape.dtb
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cape-cdp-overlay.dtbo-base := cape.dtb
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cape-atp-overlay.dtbo-base := cape.dtb
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else
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dtb-$(CONFIG_ARCH_CAPE) += cape-mtp.dtb \
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cape-cdp.dtb \
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cape-atp.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo
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dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
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11
qcom/cape-atp-overlay.dts
Normal file
11
qcom/cape-atp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "cape-atp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape ATP";
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compatible = "qcom,cape-atp", "qcom,cape", "qcom,atp";
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qcom,msm-id = <530 0x10000>;
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qcom,board-id = <33 0>;
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};
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10
qcom/cape-atp.dts
Normal file
10
qcom/cape-atp.dts
Normal file
@@ -0,0 +1,10 @@
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/dts-v1/;
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#include "cape.dtsi"
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#include "cape-atp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape ATP";
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compatible = "qcom,cape-atp", "qcom,cape", "qcom,atp";
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qcom,board-id = <33 0>;
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};
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1
qcom/cape-atp.dtsi
Normal file
1
qcom/cape-atp.dtsi
Normal file
@@ -0,0 +1 @@
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&soc { };
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11
qcom/cape-cdp-overlay.dts
Normal file
11
qcom/cape-cdp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "cape-cdp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape CDP";
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compatible = "qcom,cape-cdp", "qcom,cape", "qcom,cdp";
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qcom,msm-id = <530 0x10000>;
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qcom,board-id = <1 0>;
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};
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10
qcom/cape-cdp.dts
Normal file
10
qcom/cape-cdp.dts
Normal file
@@ -0,0 +1,10 @@
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/dts-v1/;
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#include "cape.dtsi"
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#include "cape-cdp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape CDP";
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compatible = "qcom,cape-cdp", "qcom,cape", "qcom,cdp";
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qcom,board-id = <1 0>;
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};
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1
qcom/cape-cdp.dtsi
Normal file
1
qcom/cape-cdp.dtsi
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@@ -0,0 +1 @@
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&soc { };
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12
qcom/cape-mtp-overlay.dts
Normal file
12
qcom/cape-mtp-overlay.dts
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@@ -0,0 +1,12 @@
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/dts-v1/;
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/plugin/;
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#include "cape-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape MTP";
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compatible = "qcom,cape-mtp", "qcom,cape", "qcom,mtp";
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qcom,msm-id = <530 0x10000>;
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qcom,board-id = <8 0>;
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};
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10
qcom/cape-mtp.dts
Normal file
10
qcom/cape-mtp.dts
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@@ -0,0 +1,10 @@
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/dts-v1/;
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#include "cape.dtsi"
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#include "cape-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape MTP";
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compatible = "qcom,cape-mtp", "qcom,cape", "qcom,mtp";
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qcom,board-id = <8 0>;
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};
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1
qcom/cape-mtp.dtsi
Normal file
1
qcom/cape-mtp.dtsi
Normal file
@@ -0,0 +1 @@
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&soc { };
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9
qcom/cape.dts
Normal file
9
qcom/cape.dts
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@@ -0,0 +1,9 @@
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/dts-v1/;
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#include "cape.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Cape SoC";
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compatible = "qcom,cape";
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qcom,board-id = <0 0>;
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};
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260
qcom/cape.dtsi
Normal file
260
qcom/cape.dtsi
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@@ -0,0 +1,260 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Cape";
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compatible = "qcom,cape";
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qcom,msm-id = <530 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen: chosen { };
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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aliases { };
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firmware: firmware { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_0>; /* silver L2 sharing */
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_2>; /* silver L2 sharing */
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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};
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&firmware {
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qcom_scm {
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compatible = "qcom,scm";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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};
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