Merge "ARM: dts: msm: Add ipcc Node for Cape"

bindings/arm/msm/msm.txt

@@ -92,6 +92,9 @@ SoCs:
 - DIWALI
   compatible = "qcom,diwali"
 
+- CAPE
+  compatible = "qcom,cape"
+
 - NEO
   compatible = "qcom,neo"
 
@@ -257,6 +260,9 @@ compatible = "qcom,waipiop-hdk"
 compatible = "qcom,waipiop-mtp"
 compatible = "qcom,waipiop-cdp"
 compatible = "qcom,waipiop-qrd"
+compatible = "qcom,cape-mtp"
+compatible = "qcom,cape-atp"
+compatible = "qcom,cape-cdp"
 compatible = "qcom,diwali-rumi"
 compatible = "qcom,diwali-idp"
 compatible = "qcom,diwali-qrd"

bindings/pinctrl/qcom,cape-pinctrl.yaml

@@ -0,0 +1,182 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,cape-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CAPE TLMM block
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  CAPE platform.
+
+properties:
+  compatible:
+      Usage: required
+      Value type: <string>
+      Definition: must be "qcom,cape-pinctrl"
+
+  reg:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: the base address and size of the TLMM register space.
+
+  interrupts:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: should specify the TLMM summary IRQ.
+
+  interrupt-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as an interrupt controller
+
+  #interrupt-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/interrupt-controller/irq.h>
+
+  gpio-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as a gpio controller
+
+  #gpio-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/gpio/gpio.h>
+
+  wakeup-parent:
+      Usage: optional
+      Value type: <phandle>
+      Definition: A phandle to the wakeup interrupt controller for the SoC.
+
+  Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+  a general description of GPIO and interrupt bindings.
+
+  Please refer to pinctrl-bindings.txt in this directory for details of the
+  common pinctrl bindings used by client devices, including the meaning of the
+  phrase "pin configuration node".
+
+  The pin configuration nodes act as a container for an arbitrary number of
+  subnodes. Each of these subnodes represents some desired configuration for a
+  pin, a group, or a list of pins or groups. This configuration can include the
+  mux function to select on those pin(s)/group(s), and various pin configuration
+  parameters, such as pull-up, drive strength, etc.
+
+
+  PIN CONFIGURATION NODES:
+
+  The name of each subnode is not important; all subnodes should be enumerated
+  and processed purely based on their content.
+
+  Each subnode only affects those parameters that are explicitly listed. In
+  other words, a subnode that lists a mux function but no pin configuration
+  parameters implies no information about any pin configuration parameters.
+  Similarly, a pin subnode that describes a pullup parameter implies no
+  information about e.g. the mux function.
+
+
+  The following generic properties as defined in pinctrl-bindings.txt are valid
+  to specify in a pin configuration subnode:
+
+  pins:
+        Usage: required
+        Value type: <string-array>
+        Definition: List of gpio pins affected by the properties specified in
+                    this subnode.
+
+        Valid pins:
+                  gpio0-gpio169
+                  Supports mux, bias and drive-strength
+
+                  sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
+                  Supports bias and drive-strength
+
+  function:
+        Usage: required
+        Value type: <string>
+        Definition: Specify the alternative function to be configured for the
+                    specified pins. Functions are only valid for gpio pins.
+        Valid values:
+		gpio, atest_char, atest_char0, atest_char1, atest_char2,
+		atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
+		atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
+		cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+		cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
+		cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+		dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
+		jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+		mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
+		mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
+		mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
+		phase_flag0, phase_flag1, phase_flag10, phase_flag11,
+		phase_flag12, phase_flag13, phase_flag14, phase_flag15,
+		phase_flag16, phase_flag17, phase_flag18, phase_flag19,
+		phase_flag2, phase_flag20, phase_flag21, phase_flag22,
+		phase_flag23, phase_flag24, phase_flag25, phase_flag26,
+		phase_flag27, phase_flag28, phase_flag29, phase_flag3,
+		phase_flag30, phase_flag31, phase_flag4, phase_flag5,
+		phase_flag6, phase_flag7, phase_flag8, phase_flag9,
+		pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
+		prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
+		qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
+		qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
+		qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
+		qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
+		qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
+		qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
+		qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
+		qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
+		tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
+		tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
+		uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
+		uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
+		vsense_trigger
+
+  bias-disable:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as no pull.
+
+  bias-pull-down:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull down.
+
+  bias-pull-up:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull up.
+
+  output-high:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven high.
+                  Not valid for sdc pins.
+
+  output-low:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven low.
+                  Not valid for sdc pins.
+
+  drive-strength:
+    Usage: optional
+    Value type: <u32>
+    Definition: Selects the drive strength for the specified pins, in mA.
+    Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
+
+examples:
+  - |
+    tlmm: pinctrl@f000000 {
+      compatible = "qcom,cape-pinctrl";
+      reg = <0x0F000000 0x1000000>;
+      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
+

qcom/Makefile

@@ -172,6 +172,20 @@ dtb-$(CONFIG_ARCH_DIWALI) += diwali-rumi.dtb \
 	diwali-qrd.dtsi
 endif
 
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+dtbo-$(CONFIG_ARCH_CAPE) += cape-mtp-overlay.dtbo \
+        cape-cdp-overlay.dtbo \
+        cape-atp-overlay.dtbo
+
+cape-mtp-overlay.dtbo-base := cape.dtb
+cape-cdp-overlay.dtbo-base := cape.dtb
+cape-atp-overlay.dtbo-base := cape.dtb
+else
+dtb-$(CONFIG_ARCH_CAPE) += cape-mtp.dtb \
+        cape-cdp.dtb \
+        cape-atp.dtb
+endif
+
 ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
 	dtbo-$(CONFIG_ARCH_HOLI) +=  holi-rumi-overlay.dtbo
 dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \

qcom/cape-atp-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "cape-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape ATP";
+	compatible = "qcom,cape-atp", "qcom,cape", "qcom,atp";
+	qcom,msm-id = <530 0x10000>;
+	qcom,board-id = <33 0>;
+};

qcom/cape-atp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "cape.dtsi"
+#include "cape-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape ATP";
+	compatible = "qcom,cape-atp", "qcom,cape", "qcom,atp";
+	qcom,board-id = <33 0>;
+};

qcom/cape-atp.dtsi

@@ -0,0 +1 @@
+&soc { };

qcom/cape-cdp-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "cape-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape CDP";
+	compatible = "qcom,cape-cdp", "qcom,cape", "qcom,cdp";
+	qcom,msm-id = <530 0x10000>;
+	qcom,board-id = <1 0>;
+};

qcom/cape-cdp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "cape.dtsi"
+#include "cape-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape CDP";
+	compatible = "qcom,cape-cdp", "qcom,cape", "qcom,cdp";
+	qcom,board-id = <1 0>;
+};

qcom/cape-cdp.dtsi

@@ -0,0 +1 @@
+&soc { };

qcom/cape-mtp-overlay.dts

@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "cape-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape MTP";
+	compatible = "qcom,cape-mtp", "qcom,cape", "qcom,mtp";
+	qcom,msm-id = <530 0x10000>;
+	qcom,board-id = <8 0>;
+};
+

qcom/cape-mtp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "cape.dtsi"
+#include "cape-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape MTP";
+	compatible = "qcom,cape-mtp", "qcom,cape", "qcom,mtp";
+	qcom,board-id = <8 0>;
+};

qcom/cape-mtp.dtsi

@@ -0,0 +1 @@
+&soc { };

qcom/cape-pinctrl.dtsi

@@ -0,0 +1 @@
+&tlmm { };

qcom/cape.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "cape.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape SoC";
+	compatible = "qcom,cape";
+	qcom,board-id = <0 0>;
+};

qcom/cape.dtsi

@@ -0,0 +1,281 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape";
+	compatible = "qcom,cape";
+	qcom,msm-id = <530 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen: chosen { };
+
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	reserved_memory: reserved-memory { };
+
+	aliases { };
+
+	firmware: firmware { };
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+					compatible = "arm,arch-cache";
+					cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>; /* silver L2 sharing */
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>; /* silver L2 sharing */
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	soc: soc { };
+};
+
+&firmware {
+	qcom_scm {
+		compatible = "qcom,scm";
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@17100000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x17100000 0x10000>,	/* GICD */
+		      <0x17180000 0x200000>;	/* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,cape-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@17420000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17420000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17421000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17421000 0x1000>,
+			      <0x17422000 0x1000>;
+		};
+
+		frame@17423000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17423000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17425000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17425000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17427000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17427000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17429000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17429000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	ipcc_mproc: qcom,ipcc@ed18000 {
+		compatible = "qcom,ipcc";
+		reg = <0xed18000 0x1000>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
+};
+
+#include "cape-pinctrl.dtsi"