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ARM: dts: msm: Update Graphics and Camera clock nodes for DIWALI

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Update the Graphics and Camera clock controller nodes. While at it,
move the GDSC nodes of Camera, Graphics and Video to real from dummy
for DIWALI platform.

Change-Id: Ib254f1791e45cb3087de3a95a3e21c4f7161477f
This commit is contained in:
Jagadeesh Kona
2021-06-22 12:09:24 +05:30
parent decbd414b5
commit 317d629440
3 changed files with 124 additions and 24 deletions
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74
qcom/diwali-gdsc.dtsi
View File

@@ -1,7 +1,7 @@
&soc {
/* CAM_CC GDSCs */
cam_cc_bps_gdsc: qcom,gdsc@ad10004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad10004 0x4>;
regulator-name = "cam_cc_bps_gdsc";
qcom,retain-regs;
@@ -10,7 +10,7 @@
};
cam_cc_ife_0_gdsc: qcom,gdsc@ad13004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad13004 0x4>;
regulator-name = "cam_cc_ife_0_gdsc";
qcom,retain-regs;
@@ -18,7 +18,7 @@
};
cam_cc_ife_1_gdsc: qcom,gdsc@ad14004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad14004 0x4>;
regulator-name = "cam_cc_ife_1_gdsc";
qcom,retain-regs;
@@ -26,7 +26,7 @@
};
cam_cc_ife_2_gdsc: qcom,gdsc@ad14078 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad14078 0x4>;
regulator-name = "cam_cc_ife_2_gdsc";
qcom,retain-regs;
@@ -34,7 +34,7 @@
};
cam_cc_ipe_0_gdsc: qcom,gdsc@ad11004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad11004 0x4>;
regulator-name = "cam_cc_ipe_0_gdsc";
qcom,retain-regs;
@@ -43,7 +43,7 @@
};
cam_cc_titan_top_gdsc: qcom,gdsc@ad15120 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xad15120 0x4>;
regulator-name = "cam_cc_titan_top_gdsc";
qcom,retain-regs;
@@ -172,53 +172,87 @@
status = "disabled";
};
/* GPU_CC GDSCs */
gpu_cc_cx_hw_ctrl: syscon@3d9953c {
compatible = "syscon";
reg = <0x3d9953c 0x4>;
};
/* GPU_CC GDSCs */
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x3d99108 0x4>;
hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
regulator-name = "gpu_cc_cx_gdsc";
qcom,no-status-check-on-disable;
qcom,clk-dis-wait-val = <8>;
qcom,retain-regs;
status = "disabled";
};
gpu_cc_gx_domain_addr: syscon@3d99504 {
compatible = "syscon";
reg = <0x3d99504 0x4>;
};
gpu_cc_gx_sw_reset: syscon@3d99058 {
compatible = "syscon";
reg = <0x3d99058 0x4>;
};
gpu_cc_gx_acd_reset: syscon@3d99358 {
compatible = "syscon";
reg = <0x3d99358 0x4>;
};
gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
compatible = "syscon";
reg = <0x3d9958c 0x4>;
};
gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x3d9905c 0x4>;
regulator-name = "gpu_cc_gx_gdsc";
domain-addr = <&gpu_cc_gx_domain_addr>;
sw-reset = <&gpu_cc_gx_sw_reset>,
<&gpu_cc_gx_acd_reset>,
<&gpu_cc_gx_acd_iroot_reset>;
qcom,reset-aon-logic;
qcom,retain-regs;
status = "disabled";
};
/* VIDEO_CC GDSCs */
video_cc_mvs0_gdsc: qcom,gdsc@abf81a4 {
compatible = "regulator-fixed";
reg = <0xabf81a4 0x4>;
video_cc_mvs0_gdsc: qcom,gdsc@aaf81a4 {
compatible = "qcom,gdsc";
reg = <0xaaf81a4 0x4>;
regulator-name = "video_cc_mvs0_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
status = "disabled";
};
video_cc_mvs0c_gdsc: qcom,gdsc@abf8084 {
compatible = "regulator-fixed";
reg = <0xabf8084 0x4>;
video_cc_mvs0c_gdsc: qcom,gdsc@aaf8084 {
compatible = "qcom,gdsc";
reg = <0xaaf8084 0x4>;
regulator-name = "video_cc_mvs0c_gdsc";
qcom,retain-regs;
status = "disabled";
};
video_cc_mvs1_gdsc: qcom,gdsc@abf8244 {
compatible = "regulator-fixed";
reg = <0xabf8244 0x4>;
video_cc_mvs1_gdsc: qcom,gdsc@aaf8244 {
compatible = "qcom,gdsc";
reg = <0xaaf8244 0x4>;
regulator-name = "video_cc_mvs1_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
status = "disabled";
};
video_cc_mvs1c_gdsc: qcom,gdsc@abf8124 {
compatible = "regulator-fixed";
reg = <0xabf8124 0x4>;
video_cc_mvs1c_gdsc: qcom,gdsc@aaf8124 {
compatible = "qcom,gdsc";
reg = <0xaaf8124 0x4>;
regulator-name = "video_cc_mvs1c_gdsc";
qcom,retain-regs;
status = "disabled";

14
qcom/diwali-rumi.dtsi
View File

@@ -1,3 +1,4 @@
#include <dt-bindings/clock/qcom,gcc-diwali.h>
&soc {
timer {
@@ -77,3 +78,16 @@
maximum-speed = "high-speed";
};
};
&gpucc {
clocks = <&bi_tcxo>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
};
&camcc {
clocks = <&bi_tcxo>,
<&bi_tcxo_ao>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
};

60
qcom/diwali.dtsi
View File

@@ -654,8 +654,17 @@
};
camcc: clock-controller@ad00000 {
compatible = "qcom,dummycc";
clock-output-names = "camcc_clocks";
compatible = "qcom,diwali-camcc", "syscon";
reg = <0xad00000 0x20000>;
reg-name = "cc_base";
vdd_cam_cx-supply = <&VDD_CAM_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -686,8 +695,15 @@
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
compatible = "qcom,diwali-gpucc", "syscon";
reg = <0x3d90000 0xA000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -1279,26 +1295,44 @@
#include "ipcc-test-diwali.dtsi"
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
&cam_cc_ife_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
&cam_cc_ife_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
&cam_cc_ife_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
&cam_cc_ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
&cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CAM_CX_LEVEL>;
status = "ok";
};
@@ -1366,26 +1400,44 @@
};
&gpu_cc_cx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_cc_gx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
status = "ok";
};
&video_cc_mvs0_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&video_cc_mvs0c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&video_cc_mvs1_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&video_cc_mvs1c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
#include "diwali-stub-regulator.dtsi"