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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Add the lahaina gpu dtsi
This adds the devicetree node for the lahaina gpu device. Change-Id: I379fad5c7b5ee94acd1b94e3d201f70449ac41ba
This commit is contained in:
Harshdeep Dhatt
214
qcom/lahaina-gpu.dtsi
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214
qcom/lahaina-gpu.dtsi
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@@ -0,0 +1,214 @@
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a660_zap";
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memory-region = <&pil_gpu_mem>;
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};
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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compatible = "qcom,kgsl-3d0";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
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<0x3de0000 0x10000>, <0x3d8b000 0x2000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
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"isense_cntl";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,chipid = <0x06060000>;
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qcom,initial-pwrlevel = <2>;
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qcom,no-nap;
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qcom,highest-bank-bit = <16>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <4>;
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconntect-names = "gpu_icc_path";
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qcom,bus-table-ddr7 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 */
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<MHZ_TO_KBPS(451, 4)>, /* index=2 */
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<MHZ_TO_KBPS(547, 4)>, /* index=3 */
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<MHZ_TO_KBPS(681, 4)>, /* index=4 */
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<MHZ_TO_KBPS(768, 4)>, /* index=5 */
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<MHZ_TO_KBPS(1017, 4)>, /* index=6 */
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<MHZ_TO_KBPS(1353, 4)>, /* index=7 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=8 */
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<MHZ_TO_KBPS(1708, 4)>, /* index=9 */
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<MHZ_TO_KBPS(2092, 4)>; /* index=10 */
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qcom,bus-table-ddr8 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 */
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<MHZ_TO_KBPS(451, 4)>, /* index=2 */
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<MHZ_TO_KBPS(547, 4)>, /* index=3 */
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<MHZ_TO_KBPS(681, 4)>, /* index=4 */
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<MHZ_TO_KBPS(768, 4)>, /* index=5 */
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<MHZ_TO_KBPS(1017, 4)>, /* index=6 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=7 */
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<MHZ_TO_KBPS(1708, 4)>, /* index=8 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=9 */
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<MHZ_TO_KBPS(2736, 4)>, /* index=10 */
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<MHZ_TO_KBPS(3196, 4)>; /* index=11 */
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <540000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <1>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <443000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <1>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <315000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <1>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x03da0000 0x20000>;
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clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb";
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_lpac: gfx3d_lpac {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x1 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x400>;
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qcom,iommu-dma = "disabled";
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};
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};
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gmu: qcom,gmu@3d69000 {
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compatible = "qcom,gpu-gmu";
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reg = <0x3d6a000 0x30000>,
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<0xb290000 0x10000>;
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reg-names = "kgsl_gmu_reg",
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"kgsl_gmu_pdc_cfg";
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
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regulator-names = "vddcx", "vdd";
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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vdd-supply = <&gpu_cc_gx_gdsc>;
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clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "ahb_clk", "hub_clk";
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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gmu_user: gmu_user {
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compatible = "qcom,smmu-gmu-user-cb";
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iommus = <&kgsl_smmu 0x4 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gmu_kernel: gmu_kernel {
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compatible = "qcom,smmu-gmu-kernel-cb";
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iommus = <&kgsl_smmu 0x5 0x400>;
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qcom,iommu-dma = "disabled";
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};
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};
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};
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@@ -2941,3 +2941,4 @@
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#include "lahaina-vidc.dtsi"
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#include "lahaina-cvp.dtsi"
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#include "lahaina-pcie.dtsi"
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#include "lahaina-gpu.dtsi"
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