Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add support for CPUFREQ-HW and CPUFREQ-HW-DEBUG

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Add cpu frequency node to be able to scale the CPU frequency.
Also add support for CPUFREQ-HW-DEBUG node to dump the EPSS registers
for debugging.

Change-Id: I56b25d64e5b08d7f3e42f1dc9155b29dc8f9237c
This commit is contained in:
Anaadi Mishra
2022-06-16 17:27:41 +05:30
parent b06929bb35
commit 59d625ba92
2 changed files with 32 additions and 1 deletions
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4
qcom/anorak-rumi.dtsi
View File

@@ -235,3 +235,7 @@
status = "ok";
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};

29
qcom/anorak.dtsi
View File

@@ -27,7 +27,7 @@
chosen: chosen {
bootargs = "console=ttyMSM0,115200n8 earlycon=msm_geni_serial,0x00998000 loglevel=8 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 service_locator.enable=1 msm_rtb.filter=0x237 allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-5 ftrace_dump_on_oops pstore.compress=none kpti=off swiotlb=noforce cgroup.memory=nokmem,nosocket allow_file_spec_access can.stats_timer=0 disable_dma32=on";
bootargs = "console=ttyMSM0,115200n8 earlycon=msm_geni_serial,0x00998000 loglevel=8 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 service_locator.enable=1 msm_rtb.filter=0x237 allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-5 ftrace_dump_on_oops pstore.compress=none kpti=off swiotlb=noforce cgroup.memory=nokmem,nosocket allow_file_spec_access can.stats_timer=0 disable_dma32=on cpufreq.default_governor=performance";
};
ddr-regions { };
@@ -66,6 +66,7 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -90,6 +91,7 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -110,6 +112,7 @@
capacity-dmips-mhz = <1075>;
dynamic-power-coefficient = <109>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -129,6 +132,7 @@
capacity-dmips-mhz = <1075>;
dynamic-power-coefficient = <109>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -149,6 +153,7 @@
capacity-dmips-mhz = <1075>;
dynamic-power-coefficient = <109>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -168,6 +173,7 @@
capacity-dmips-mhz = <1075>;
dynamic-power-coefficient = <109>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -491,6 +497,27 @@
interrupt-controller;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x17d91000 0x1000>,
<0x17d92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
};
apps_rsc: rsc@17a00000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";