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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add audio specific dt files for shima
Add audio specific dt files for shima as part of initial changes. Change-Id: I2e20db99b186f38cf2c52c7d344dad617b2d63d6
This commit is contained in:
Vatsal Bucha
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
051eca5eb5
commit
64fe73877a
@@ -66,6 +66,8 @@ Optional properties:
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- qcom,va-clk-mux-selectï¼ VA macro MCLK MUX selection
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- qcom,va-island-mode-muxselï¼ VA macro island mode MUX selection
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This property is required if qcom,va-clk-mux-select is provided
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- qcom,disable-afe-wakeup-event-listener : If enabled wakeup event listener
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will not be called from VA macro.
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Example:
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411
qcom/shima-audio-overlay.dtsi
Normal file
411
qcom/shima-audio-overlay.dtsi
Normal file
@@ -0,0 +1,411 @@
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#include <dt-bindings/clock/qcom,audio-ext-clk.h>
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#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
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#include <dt-bindings/sound/audio-codec-port-types.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&bolero {
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qcom,num-macros = <4>;
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qcom,bolero-version = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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bolero-clk-rsc-mngr {
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compatible = "qcom,bolero-clk-rsc-mngr";
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qcom,fs-gen-sequence = <0x3000 0x1>,
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<0x3004 0x1>, <0x3080 0x2>;
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qcom,rx_mclk_mode_muxsel = <0x033240D8>;
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qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
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qcom,va_mclk_mode_muxsel = <0x033A0000>;
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clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
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"wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
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clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
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<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
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<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
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<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
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};
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va_macro: va-macro@3370000 {
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compatible = "qcom,va-macro";
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reg = <0x3370000 0x0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,va-vdd-micb-voltage = <1800000 1800000>;
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qcom,va-vdd-micb-current = <11200>;
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qcom,va-dmic-sample-rate = <600000>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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qcom,is-used-swr-gpio = <0>;
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qcom,disable-afe-wakeup-event-listener = <1>;
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};
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tx_macro: tx-macro@3220000 {
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compatible = "qcom,tx-macro";
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reg = <0x3220000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>,
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<&clock_audio_tx_2 0>;
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qcom,tx-swr-gpios = <&tx_swr_gpios>;
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qcom,tx-dmic-sample-rate = <2400000>;
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swr2: tx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <3>;
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qcom,swrm-hctl-reg = <0x032a90a8>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x3230000 0x0>;
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interrupts-extended =
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<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq", "swr_wake_irq";
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qcom,swr-num-ports = <3>;
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qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,
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<1 SWRM_TX1_CH2 0x2>,
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<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,
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<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,
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<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,
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<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
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<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-mstr-irq-wakeup-capable = <1>;
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wcd938x_tx_slave: wcd938x-tx-slave {
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compatible = "qcom,wcd938x-slave";
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reg = <0x0D 0x01170223>;
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};
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};
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};
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rx_macro: rx-macro@3200000 {
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compatible = "qcom,rx-macro";
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reg = <0x3200000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x033240D8>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <2>;
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qcom,swrm-hctl-reg = <0x032a90a0>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x3210000 0x0>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <6>;
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qcom,swr-port-mapping = <1 HPH_L 0x1>,
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<1 HPH_R 0x2>, <2 CLSH 0x1>,
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<3 COMP_L 0x1>, <3 COMP_R 0x2>,
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<4 LO 0x1>, <5 DSD_L 0x1>,
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<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>;
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qcom,swr-num-dev = <2>;
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qcom,swr-clock-stop-mode0 = <1>;
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swr_haptics: swr_haptics@f0170220 {
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compatible = "qcom,pm8350b-swr-haptics";
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reg = <0x01 0xf0170220>;
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swr-slave-supply = <&hap_swr_slave_reg>;
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qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
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};
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wcd938x_rx_slave: wcd938x-rx-slave {
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compatible = "qcom,wcd938x-slave";
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reg = <0x0D 0x01170224>;
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};
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};
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};
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wsa_macro: wsa-macro@3240000 {
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compatible = "qcom,wsa-macro";
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reg = <0x3240000 0x0>;
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clock-names = "wsa_core_clk", "wsa_npl_clk";
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clocks = <&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>;
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qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr_master_id = <1>;
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qcom,swrm-hctl-reg = <0x032a90b0>;
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qcom,mipi-sdw-block-packing-mode = <0>;
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swrm-io-base = <0x3250000 0x0>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <8>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-port-mapping = <1 SPKR_L 0x1>,
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<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
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<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
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<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
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<8 SPKR_R_VI 0x3>;
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qcom,swr-num-dev = <2>;
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qcom,dynamic-port-map-supported = <0>;
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wsa883x_0221: wsa883x@02170221 {
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compatible = "qcom,wsa883x";
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reg = <0x2 0x2170221>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
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qcom,bolero-handle = <&bolero>;
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cdc-vdd-1p8-supply = <&S10B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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qcom,wsa-prefix = "SpkrLeft";
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};
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wsa883x_0222: wsa883x@02170222 {
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compatible = "qcom,wsa883x";
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reg = <0x2 0x2170222>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
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qcom,bolero-handle = <&bolero>;
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cdc-vdd-1p8-supply = <&S10B>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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qcom,wsa-prefix = "SpkrRight";
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};
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};
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};
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wcd938x_codec: wcd938x-codec {
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compatible = "qcom,wcd938x-codec";
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qcom,split-codec = <1>;
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
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<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
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<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
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<4 DSD_R 0x2 0 DSD_R>;
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qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
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<0 ADC2 0x2 0 SWRM_TX1_CH2>,
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<1 ADC3 0x1 0 SWRM_TX2_CH1>,
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<1 ADC4 0x2 0 SWRM_TX2_CH2>,
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<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
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<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
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<2 MBHC 0x4 0 SWRM_TX2_CH3>,
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<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
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<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
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<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
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<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
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<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
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<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
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qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
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qcom,rx-slave = <&wcd938x_rx_slave>;
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qcom,tx-slave = <&wcd938x_tx_slave>;
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cdc-vdd-rxtx-supply = <&S10B>;
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qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
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qcom,cdc-vdd-rxtx-current = <30000>;
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cdc-vddio-supply = <&S10B>;
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qcom,cdc-vddio-voltage = <1800000 1800000>;
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qcom,cdc-vddio-current = <30000>;
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cdc-vdd-buck-supply = <&S10B>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-vdd-mic-bias-supply = <&BOB>;
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qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
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qcom,cdc-vdd-mic-bias-current = <30000>;
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qcom,cdc-micbias1-mv = <1800>;
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qcom,cdc-micbias2-mv = <1800>;
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qcom,cdc-micbias3-mv = <1800>;
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qcom,cdc-micbias4-mv = <1800>;
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qcom,cdc-static-supplies = "cdc-vdd-rxtx",
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"cdc-vddio",
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"cdc-vdd-mic-bias";
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qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
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};
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};
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&shima_snd {
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qcom,model = "shima-mtp-snd-card";
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qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
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qcom,wcn-bt = <0>;
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qcom,ext-disp-audio-rx = <0>;
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qcom,audio-routing =
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"AMIC1", "Analog Mic1",
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"Analog Mic1", "MIC BIAS3",
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"AMIC2", "Analog Mic2",
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"Analog Mic2", "MIC BIAS2",
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"AMIC3", "Analog Mic3",
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"Analog Mic3", "MIC BIAS3",
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"AMIC4", "Analog Mic4",
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"Analog Mic4", "MIC BIAS1",
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"AMIC5", "Analog Mic5",
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"Analog Mic5", "MIC BIAS4",
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"TX DMIC0", "Digital Mic0",
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"TX DMIC0", "MIC BIAS3",
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"TX DMIC1", "Digital Mic1",
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"TX DMIC1", "MIC BIAS3",
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"TX DMIC2", "Digital Mic2",
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"TX DMIC2", "MIC BIAS1",
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"TX DMIC3", "Digital Mic3",
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"TX DMIC3", "MIC BIAS1",
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"TX DMIC4", "Digital Mic4",
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"TX DMIC4", "MIC BIAS4",
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"TX DMIC5", "Digital Mic5",
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"TX DMIC5", "MIC BIAS4",
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"IN1_HPHL", "HPHL_OUT",
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"IN2_HPHR", "HPHR_OUT",
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"IN3_AUX", "AUX_OUT",
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"HAP_IN", "PCM_OUT",
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"WSA SRC0_INP", "SRC0",
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"WSA_TX DEC0_INP", "TX DEC0 MUX",
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"WSA_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC0_INP", "TX DEC0 MUX",
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"RX_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC2_INP", "TX DEC2 MUX",
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"RX_TX DEC3_INP", "TX DEC3 MUX",
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"SpkrLeft IN", "WSA_SPK1 OUT",
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"SpkrRight IN", "WSA_SPK2 OUT",
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"TX SWR_INPUT", "WCD_TX_OUTPUT",
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"VA SWR_INPUT", "VA_SWR_CLK",
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"VA SWR_INPUT", "WCD_TX_OUTPUT",
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"VA_AIF1 CAP", "VA_SWR_CLK",
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"VA_AIF2 CAP", "VA_SWR_CLK",
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"VA_AIF3 CAP", "VA_SWR_CLK",
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"VA DMIC0", "Digital Mic0",
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"VA DMIC1", "Digital Mic1",
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"VA DMIC2", "Digital Mic2",
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"VA DMIC3", "Digital Mic3",
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"VA DMIC4", "Digital Mic4",
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"VA DMIC5", "Digital Mic5",
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"VA DMIC0", "VA MIC BIAS3",
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"VA DMIC1", "VA MIC BIAS3",
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"VA DMIC2", "VA MIC BIAS1",
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"VA DMIC3", "VA MIC BIAS1",
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"VA DMIC4", "VA MIC BIAS4",
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"VA DMIC5", "VA MIC BIAS4";
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qcom,msm-mbhc-hphl-swh = <1>;
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qcom,msm-mbhc-gnd-swh = <1>;
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qcom,swr-dmic-max-devs = <0>;
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qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
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qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
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qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
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asoc-codec = <&stub_codec>, <&bolero>,
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<&wcd938x_codec>, <&swr_haptics>,
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<&wsa883x_0221>, <&wsa883x_0222>,
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<&ext_disp_audio_codec>;
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asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
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"wcd938x_codec", "swr-haptics",
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"wsa-codec1", "wsa-codec2",
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"msm-ext-disp-audio-codec-rx";
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qcom,wsa-max-devs = <2>;
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qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
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<&bolero>;
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};
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&va_cdc_dma_0_tx {
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qcom,msm-dai-is-island-supported = <1>;
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};
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&soc {
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wsa_spkr_en1: wsa_spkr_en1_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&spkr_1_sd_n_active>;
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pinctrl-1 = <&spkr_1_sd_n_sleep>;
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};
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wsa_spkr_en2: wsa_spkr_en2_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&spkr_2_sd_n_active>;
|
||||
pinctrl-1 = <&spkr_2_sd_n_sleep>;
|
||||
};
|
||||
|
||||
wcd938x_rst_gpio: msm_cdc_pinctrl@35 {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wcd938x_reset_active>;
|
||||
pinctrl-1 = <&wcd938x_reset_sleep>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_1: wsa_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x309>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_wsa_2: wsa_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30A>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_1: rx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30E>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_rx_2: rx_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
|
||||
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
||||
qcom,codec-lpass-clk-id = <0x30F>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_1: tx_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30C>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_tx_2: tx_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30D>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_va_1: va_core_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x30B>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clock_audio_va_2: va_npl_clk {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
|
||||
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
||||
qcom,codec-lpass-clk-id = <0x310>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
256
qcom/shima-audio.dtsi
Normal file
256
qcom/shima-audio.dtsi
Normal file
@@ -0,0 +1,256 @@
|
||||
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
|
||||
#include "msm-audio-lpass.dtsi"
|
||||
|
||||
&msm_audio_ion {
|
||||
iommus = <&apps_smmu 0x2001 0x0>;
|
||||
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
|
||||
};
|
||||
|
||||
&audio_apr {
|
||||
q6core: qcom,q6core-audio {
|
||||
compatible = "qcom,q6core-audio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
lpass_core_hw_vote: vote_lpass_core_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_audio_hw_vote: vote_lpass_audio_hw {
|
||||
compatible = "qcom,audio-ref-clk";
|
||||
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
lpi_tlmm: lpi_pinctrl@33c0000 {
|
||||
compatible = "qcom,lpi-pinctrl";
|
||||
reg = <0x33c0000 0x0>;
|
||||
qcom,slew-reg = <0x355a000 0x0>;
|
||||
qcom,gpios-count = <15>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
|
||||
<0x00002000>, <0x00003000>,
|
||||
<0x00004000>, <0x00005000>,
|
||||
<0x00006000>, <0x00007000>,
|
||||
<0x00008000>, <0x00009000>,
|
||||
<0x0000A000>, <0x0000B000>,
|
||||
<0x0000C000>, <0x0000D000>,
|
||||
<0x0000E000>;
|
||||
qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
|
||||
<0x00000004>, <0x00000008>,
|
||||
<0x0000000A>, <0x0000000C>,
|
||||
<0x00000000>, <0x00000000>,
|
||||
<0x00000000>, <0x00000000>,
|
||||
<0x00000010>, <0x00000012>,
|
||||
<0x00000000>, <0x00000000>,
|
||||
<0x00000006>;
|
||||
|
||||
clock-names = "lpass_core_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>;
|
||||
};
|
||||
|
||||
bolero: bolero-cdc {
|
||||
compatible = "qcom,bolero-codec";
|
||||
clock-names = "lpass_core_hw_vote",
|
||||
"lpass_audio_hw_vote";
|
||||
clocks = <&lpass_core_hw_vote 0>,
|
||||
<&lpass_audio_hw_vote 0>;
|
||||
bolero-clk-rsc-mngr {
|
||||
compatible = "qcom,bolero-clk-rsc-mngr";
|
||||
};
|
||||
|
||||
va_macro: va-macro@3370000 {
|
||||
};
|
||||
|
||||
tx_macro: tx-macro@3220000 {
|
||||
swr2: tx_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
rx_macro: rx-macro@3200000 {
|
||||
swr1: rx_swr_master {
|
||||
};
|
||||
};
|
||||
|
||||
wsa_macro: wsa-macro@3240000 {
|
||||
swr0: wsa_swr_master {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "shima-lpi.dtsi"
|
||||
|
||||
&q6core {
|
||||
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
||||
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <179>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
||||
&rx_swr_data1_active>;
|
||||
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
||||
&rx_swr_data1_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
tx_swr_gpios: tx_swr_clk_data_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
||||
&tx_swr_data1_active &tx_swr_data2_active>;
|
||||
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
||||
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <169>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <174 175>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <177>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
|
||||
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
||||
compatible = "qcom,msm-cdc-pinctrl";
|
||||
pinctrl-names = "aud_active", "aud_sleep";
|
||||
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
||||
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
||||
qcom,lpi-gpios;
|
||||
qcom,tlmm-pins = <180>;
|
||||
#gpio-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&q6core {
|
||||
shima_snd: sound {
|
||||
compatible = "qcom,lahaina-asoc-snd";
|
||||
qcom,mi2s-audio-intf = <0>;
|
||||
qcom,auxpcm-audio-intf = <1>;
|
||||
qcom,wcn-bt = <0>;
|
||||
qcom,ext-disp-audio-rx = <0>;
|
||||
qcom,afe-rxtx-lb = <0>;
|
||||
|
||||
clock-names = "lpass_audio_hw_vote";
|
||||
clocks = <&lpass_audio_hw_vote 0>;
|
||||
|
||||
asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
|
||||
<&loopback>, <&compress>, <&hostless>,
|
||||
<&afe>, <&lsm>, <&routing>, <&compr>,
|
||||
<&pcm_noirq>;
|
||||
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
|
||||
"msm-pcm-dsp.2", "msm-voip-dsp",
|
||||
"msm-pcm-voice", "msm-pcm-loopback",
|
||||
"msm-compress-dsp", "msm-pcm-hostless",
|
||||
"msm-pcm-afe", "msm-lsm-client",
|
||||
"msm-pcm-routing", "msm-compr-dsp",
|
||||
"msm-pcm-dsp-noirq";
|
||||
asoc-cpu = <&dai_dp>, <&dai_dp1>,
|
||||
<&dai_mi2s0>, <&dai_mi2s1>,
|
||||
<&dai_mi2s2>, <&dai_mi2s3>,
|
||||
<&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>,
|
||||
<&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
|
||||
<&dai_quat_auxpcm>, <&dai_quin_auxpcm>,
|
||||
<&dai_sen_auxpcm>,
|
||||
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
|
||||
<&afe_proxy_tx>, <&incall_record_rx>,
|
||||
<&incall_record_tx>, <&incall_music_rx>,
|
||||
<&incall_music_2_rx>,
|
||||
<&afe_proxy_tx_1>,
|
||||
<&proxy_rx>, <&proxy_tx>,
|
||||
<&usb_audio_rx>, <&usb_audio_tx>,
|
||||
<&sb_7_rx>, <&sb_7_tx>,
|
||||
<&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
|
||||
<&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
|
||||
<&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
|
||||
<&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
|
||||
<&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
|
||||
<&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>,
|
||||
<&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>,
|
||||
<&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>,
|
||||
<&wsa_cdc_dma_2_tx>,
|
||||
<&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
|
||||
<&va_cdc_dma_2_tx>,
|
||||
<&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
|
||||
<&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
|
||||
<&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
|
||||
<&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
|
||||
<&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
|
||||
<&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
|
||||
<&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
|
||||
<&afe_loopback_tx>;
|
||||
asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1",
|
||||
"msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
|
||||
"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
|
||||
"msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",
|
||||
"msm-dai-q6-auxpcm.1",
|
||||
"msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
|
||||
"msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5",
|
||||
"msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224",
|
||||
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
|
||||
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
|
||||
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
|
||||
"msm-dai-q6-dev.32770",
|
||||
"msm-dai-q6-dev.242",
|
||||
"msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
|
||||
"msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
|
||||
"msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
|
||||
"msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
|
||||
"msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
|
||||
"msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
|
||||
"msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
|
||||
"msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929",
|
||||
"msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945",
|
||||
"msm-dai-cdc-dma-dev.45056",
|
||||
"msm-dai-cdc-dma-dev.45057",
|
||||
"msm-dai-cdc-dma-dev.45058",
|
||||
"msm-dai-cdc-dma-dev.45059",
|
||||
"msm-dai-cdc-dma-dev.45061",
|
||||
"msm-dai-cdc-dma-dev.45089",
|
||||
"msm-dai-cdc-dma-dev.45091",
|
||||
"msm-dai-cdc-dma-dev.45093",
|
||||
"msm-dai-cdc-dma-dev.45104",
|
||||
"msm-dai-cdc-dma-dev.45105",
|
||||
"msm-dai-cdc-dma-dev.45106",
|
||||
"msm-dai-cdc-dma-dev.45107",
|
||||
"msm-dai-cdc-dma-dev.45108",
|
||||
"msm-dai-cdc-dma-dev.45109",
|
||||
"msm-dai-cdc-dma-dev.45110",
|
||||
"msm-dai-cdc-dma-dev.45111",
|
||||
"msm-dai-cdc-dma-dev.45112",
|
||||
"msm-dai-cdc-dma-dev.45113",
|
||||
"msm-dai-cdc-dma-dev.45114",
|
||||
"msm-dai-cdc-dma-dev.45115",
|
||||
"msm-dai-cdc-dma-dev.45116",
|
||||
"msm-dai-cdc-dma-dev.45118",
|
||||
"msm-dai-q6-dev.24577";
|
||||
};
|
||||
};
|
||||
|
||||
1679
qcom/shima-lpi.dtsi
Normal file
1679
qcom/shima-lpi.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -29,6 +29,9 @@
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
|
||||
sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/
|
||||
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
|
||||
swr0 = &swr0;
|
||||
swr1 = &swr1;
|
||||
swr2 = &swr2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -2253,6 +2256,7 @@
|
||||
#include "shima-vidc.dtsi"
|
||||
#include "shima-thermal.dtsi"
|
||||
#include "shima-gpu.dtsi"
|
||||
#include "shima-audio.dtsi"
|
||||
|
||||
&gcc_pcie_0_gdsc {
|
||||
status = "ok";
|
||||
|
||||
Reference in New Issue
Block a user