Merge "ARM: dts: msm: Enable download/restart mode drivers for Cape"

This commit is contained in:
qctecmdr
2021-11-01 07:08:52 -07:00
committed by Gerrit - the friendly Code Review server
2 changed files with 79 additions and 0 deletions

View File

@@ -82,6 +82,12 @@
};
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;

View File

@@ -267,6 +267,7 @@
&firmware {
qcom_scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
@@ -943,7 +944,79 @@
clock-frequency = <32768>;
};
qcom,msm-imem@146aa000 {
compatible = "qcom,msm-imem";
reg = <0x146aa000 0x1000>;
ranges = <0x0 0x146aa000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058
0x17840058 0x17850058 0x17860058 0x17870058>;
qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060
0x17840060 0x17850060 0x17860060 0x17870060>;
};
ramoops_mem: ramoops_region {
compatible = "ramoops";
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
dload_mode {
compatible = "qcom,dload-mode";
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
};
&clock_gcc {