mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add speedbin support for parrot gpu"
This commit is contained in:
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commit
73ea8d26a5
@@ -23,8 +23,6 @@
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qcom,gpu-model = "Adreno710V1";
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qcom,initial-pwrlevel = <8>;
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qcom,no-nap;
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qcom,min-access-length = <32>;
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@@ -62,127 +60,575 @@
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<MHZ_TO_KBPS(2736, 4)>, /* index=9 */
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<MHZ_TO_KBPS(3196, 4)>; /* index=10 */
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nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
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nvmem-cell-names = "speed_bin", "gaming_bin";
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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compatible = "qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <940000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <7>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <10>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <940000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <9>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <816000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <734000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <7>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <600000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <6>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <6>;
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qcom,bus-max-ddr8 = <8>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <500000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <5>;
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <345000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <4>;
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qcom,bus-freq-ddr8 = <3>;
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qcom,bus-min-ddr8 = <3>;
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qcom,bus-max-ddr8 = <6>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <295000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <4>;
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qcom,bus-freq-ddr8 = <3>;
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qcom,bus-min-ddr8 = <3>;
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qcom,bus-max-ddr8 = <6>;
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};
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,speed-bin = <190>;
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qcom,initial-pwrlevel = <7>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <9>;
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qcom,bus-max-ddr8 = <10>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <940000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <9>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <816000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <734000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <7>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <600000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <6>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <6>;
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qcom,bus-max-ddr8 = <8>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <500000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <5>;
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <345000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <4>;
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qcom,bus-freq-ddr8 = <3>;
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qcom,bus-min-ddr8 = <3>;
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qcom,bus-max-ddr8 = <6>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <295000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <4>;
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|
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qcom,bus-freq-ddr8 = <3>;
|
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qcom,bus-min-ddr8 = <3>;
|
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qcom,bus-max-ddr8 = <6>;
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};
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <816000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,bus-freq-ddr7 = <8>;
|
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qcom,bus-min-ddr7 = <7>;
|
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qcom,bus-max-ddr7 = <8>;
|
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qcom,speed-bin = <178>;
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qcom,initial-pwrlevel = <6>;
|
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|
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qcom,bus-freq-ddr8 = <9>;
|
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qcom,bus-min-ddr8 = <8>;
|
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qcom,bus-max-ddr8 = <10>;
|
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
|
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qcom,gpu-freq = <875000000>;
|
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
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|
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qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <9>;
|
||||
qcom,bus-max-ddr8 = <10>;
|
||||
};
|
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|
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qcom,gpu-pwrlevel@1 {
|
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reg = <1>;
|
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qcom,gpu-freq = <816000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <10>;
|
||||
};
|
||||
|
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qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
qcom,speed-bin = <143>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
qcom,speed-bin = <130>;
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
qcom,bus-freq-ddr8 = <8>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
};
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <3>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -1970,6 +1970,25 @@
|
||||
shared-buffer = <&trust_ui_vm_qrtr>;
|
||||
};
|
||||
|
||||
qfprom: qfprom@221c8000 {
|
||||
compatible = "qcom,qfprom";
|
||||
reg = <0x221c8000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
ranges;
|
||||
|
||||
gpu_speed_bin: gpu_speed_bin@119 {
|
||||
reg = <0x119 0x2>;
|
||||
bits = <5 8>;
|
||||
};
|
||||
|
||||
gpu_gaming_bin: gpu_gaming_bin@130 {
|
||||
reg = <0x130 0x1>;
|
||||
bits = <6 1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,chd {
|
||||
compatible = "qcom,core-hang-detect";
|
||||
label = "core";
|
||||
|
||||
Reference in New Issue
Block a user