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bindings: regulator: gdsc: Add support for qcom,clk-ctrl bindings

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Add support for qcom,clk-ctrl bindings to enable/disable few clocks
before GDSC enable/disable.

Change-Id: Idf10902362b940e45758fcfe5aaa563a5b72d53d
This commit is contained in:
Jagadeesh Kona
2022-06-02 12:44:03 +05:30
committed by Gerrit - the friendly Code Review server
parent 75330102e6
commit 781875d23e
1 changed files with 24 additions and 0 deletions
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24
bindings/regulator/gdsc-regulator.txt
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@@ -71,6 +71,13 @@ Optional properties:
of the register.
- no-config-gdscr : Presence denotes HW only supports a single register
per GDSC.
- qcom,clk-ctrl: If present, few clocks will be enabled/disabled before the GDSC
enable/disable. This property can contain a 2D array of 4
arguments in each row, each row represents one of the clocks.First
element in row would be a phandle to the clock controller node
that contains the clk to be controlled, second would be offset
address of the clk, third would be bit number to control the
clk, fourth would be to convey if clk enable is inverted or not.
Example:
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
@@ -94,3 +101,20 @@ Example:
regulator-name = "gcc_pcie_1_gdsc";
qcom,collapse-vote = <&active_ctrl &sleep_ctrl 1>;
};
/* GDSC clock control */
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
compatible = "qcom,gdsc";
reg = <0x3d99108 0x4>;
regulator-name = "gpu_cc_cx_gdsc";
qcom,clk-ctrl = <&gpucc 0x9130 22 1>;
};
/* GDSC multiple clocks control */
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
compatible = "qcom,gdsc";
reg = <0x3d99108 0x4>;
regulator-name = "gpu_cc_cx_gdsc";
qcom,clk-ctrl = <&gpucc 0x9130 22 1>,
<&gcc 0x81018 0 0>;
};