ARM: dts: msm: Update QMP PHY register settings for parrot

This change updates the QMP PHY register settings according to
the HPG to fix receiver LFPS compliance failures observed on parrot.

Change-Id: Ib060f99b6d2bba227d31560e6e73013ef730d08d
This commit is contained in:
Pratham Pratap
2022-09-13 14:48:26 +05:30
parent 8342ac3ce1
commit 7da9be07b4

View File

@@ -210,7 +210,7 @@
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x34
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
@@ -257,7 +257,7 @@
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x34
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B