Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: add spi, i2c, gpi nodes for Ravelin SVM

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Adding spi, i2c, gsi nodes for ravelin for the trusted VM usecases.

Change-Id: Id26896594162c47e5cb2ceecf7ed81b477c16f4b
This commit is contained in:
Anil Veshala Veshala
2022-12-27 00:13:47 -08:00
parent a36d8674b2
commit 815bb23227
2 changed files with 75 additions and 5 deletions
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8
qcom/ravelin-qupv3.dtsi
View File

@@ -134,8 +134,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma0 0 1 3 64 0>,
<&gpi_dma0 1 1 3 64 0>;
dmas = <&gpi_dma0 0 1 3 64 2>,
<&gpi_dma0 1 1 3 64 2>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
@@ -156,8 +156,8 @@
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma0 0 1 1 64 0>,
<&gpi_dma0 1 1 1 64 0>;
dmas = <&gpi_dma0 0 1 1 64 2>,
<&gpi_dma0 1 1 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;

72
qcom/ravelin-vm.dtsi
View File

@@ -10,11 +10,12 @@
qcom,vm-config {
iomemory-ranges = <0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0
0x0 0x0928000 0x0 0x0928000 0x0 0x4000 0x0
0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1>;
gic-irq-ranges = <282 282>; /* PVM->SVM IRQ transfer */
vdevices {
gvsock-message-queue-pair {
status = "disabled";
@@ -66,4 +67,73 @@
/delete-node/ i2c@990000;
/delete-node/ spi@990000;
qup_iommu_group: qup_common_iommu_group {
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9c0000 0x2000>;
iommus = <&apps_smmu 0x178 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
status = "ok";
};
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x178 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,gpii-mask = <0x40>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* Legacy Touch over I2C */
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma0 0 1 3 64 0>,
<&gpi_dma0 1 1 3 64 0>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "disabled";
};
qupv3_se1_spi: spi@984000 {
compatible = "qcom,spi-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma0 0 1 1 64 0>,
<&gpi_dma0 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "disabled";
};
};