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Merge tag 'KERNEL.PLATFORM.1.0.r1-18100-kernel.0' of https://github.com/waipio-kernel-devicetree/kernel-devicetree into lineage-20

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* tag 'KERNEL.PLATFORM.1.0.r1-18100-kernel.0' of https://github.com/waipio-kernel-devicetree/kernel-devicetree:
  ARM: dts: msm: Add initial DT for AnorakP QXR HMT UFS Refgen + 4K display
  ARM: dts: msm: Add support for new WCN Card for Parrot
  ARM: dts: msm: Remove perf-lock support on ANORAK platform
  ARM: dts: msm: Add support for new WCN Card for Parrot
  dt-bindings: soc: qcom: add qcom,crypto compatible
  ARM: dts: msm: Add crypto node for neo
  Revert "ARM: dts: msm: Skip thaw during hibernate for USB"
  ARM: dts: msm: Add wlan node for qca6755 parrot
  ARM: dts: qcom: Add ParrotPRO SKU soc id support
  ARM: dts: msm: Skip thaw during hibernate for USB
  ARM: dts: msm: Add child nodes for PCIe0
  ARM: dts: msm: removing "config-recovery" and "drv-supported" for qps615
  ARM: dts: qcom: PCIe REFCLK always on
  ARM: dts: msm: Add PCIE0 node
  ARM: dts: msm: Add I2C node for PCIe switch QPS615
  ARM: dts: msm: Add dt variants for montague HSP variant
  ARM: dts: msm: Update GPU model for Ravelin gaming variants
  ARM: dts: msm: Add Gaming variant devicetree for Ravelin
  ARM: dts: msm: increase smem memory to 44k
  ARM: dts: qcom: Disable cnss-kiwi SOL on anorak platform
  ARM: dts: msm:Use st54spi_gpio dev node for stsafe320
  ARM: dts: qcom: Add Talyn devicetree support for Apache
  ARM: dts: msm: Update RC0 and RC1 PHY settings as per HSR v1.07 for neo
  ARM: dts: msm: Add stsafe320 support for montague
  ARM: dts: msm: Add device tree support for Anorak platform
  ARM: dts: msm: Add ext-region prop of cpusysvm for parrot
  ARM: dts: msm: Add support for PMD VCSEL voltage
  ARM: dts: msm: Add 788MHz GPU speed bin support for anorak
  ARM: dts: msm: increase smem memory to 44k
  ARM: dts: msm: Add power_state device for neo
  dt-bindings: soc: qcom: snapshot of DT bindings for power_state device
  ARM: dts: msm: add support for bwprof
  ARM: dts: msm: add phy aux & pll clk config1 register offset
  ARM: dts: msm: Update IPD driver for 4K Anorak SKU3

Change-Id: I2b99f955ecb8c6e6372713d462a91256ae4626c8
This commit is contained in:
Arian
2024-12-04 21:45:06 +01:00
parent e634736d52 f5c92d8ccf
commit 8a2eaef90c
159 changed files with 1917 additions and 225 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
bindings/arm/msm/msm.txt
View File

@@ -105,7 +105,7 @@ SoCs:
compatible = "qcom,parrot", "qcom,parrotp"
- ANORAK
compatible = "qcom,anorak"
compatible = "qcom,anorak", "qcom,anorakp"
- RAVELIN
compatible = "qcom,ravelin", "qcom,ravelinp"
@@ -314,6 +314,9 @@ compatible = "qcom,anorak-rumi"
compatible = "qcom,anorak-idp"
compatible = "qcom,anorak-qxr"
compatible = "qcom,anorak-atp"
compatible = "qcom,anorakp-idp"
compatible = "qcom,anorakp-qxr"
compatible = "qcom,anorakp-atp"
compatible = "qcom,ravelin-rumi"
compatible = "qcom,ravelin-atp"
compatible = "qcom,ravelin-idp"

1
bindings/cnss/icnss.txt
View File

@@ -40,6 +40,7 @@ Optional properties:
- qcom,vreg_ol_cpr: Specifies voltage regulator used for OL CPR vote
- qcom,pon-gpio-control: Boolean context flag to enable PMIC GPIO based
power sequence trigger via SPMI
- wcn-hw-version: Parameter to differentiate between different WCN HW Versions
WLAN SMP2P sub nodes

14
bindings/gpio/st,st54spi_gpio.txt Normal file
View File

@@ -0,0 +1,14 @@
ST Embedded Secure Element (eSE) GPIO
Required properties:
- compatible: "st,st54spi_gpio"
- gpio-power_nreset: GPIO pin for reset.
Example:
st54spi_gpio {
status = "ok";
compatible = "st,st54spi_gpio";
/* gpio used as SE_nRESET */
gpio-power_nreset = <&tlmm 48 0x00>;
};

74
bindings/pci/pci-msm.txt
View File

@@ -423,6 +423,17 @@ interconnects:
value type: <u32>
Definition: Offset from PCIe PHY base to dump pcie phy status registers
- qcom,phy-aux-clk-config1-offset:
Usage: required
Value type: <u32>
Definition: Offset from PCIe PHY aux clk config register to disable FLL
- qcom,phy-pll-clk-enable1-offset:
Usage: required
Value type: <u32>
Definition: ffset from PCIe PHY base to enable ext clk buf mux to
eliminate VDDA leakage
==============
Root port node
==============
@@ -587,3 +598,66 @@ Example
qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */
qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;
};
==============
i2c child node
==============
- compatible:
Usage: required
Value type: <stringlist>
Definition: Compatible list, contains
- "qcom,pcie-i2c-ntn3" for NTN3 switch attached to Root port 0
- reg:
Usage: required
Value type: <u16>
Definition: i2c slave id
- gpio-config-reg:
Usage: optional
Value type: <u32>
Definition: Slave GPIO configuration register address
- ep-reset-reg:
Usage: optional
Value type: <u32>
Definition: Slave endpoint reset register address
- ep-reset-gpio-mask:
Usage: optional
Value type: <u32>
Definition: Slave GPIO number as 32-bit mask
- dump-regs:
Usage: optional
Value Type: Array of <u32>
Definition: List of slave registers to dump by i2c read
- version-reg:
Usage: optional
Value type: <u32>
Definition: Register to find ntn3 switch version
- force-i2c-setting:
Usage: optional
Value type: <bool>
Definition: If force-i2c-setting flag is set
then de_emphasis settings are updated
irrespective of the chip version via i2c_writes
=======
Example
=======
&i2c_5 {
pcie_i2c_ctrl: pcie_i2c_ctrl {
compatible = "qcom,pcie-i2c-ntn3";
reg = <0x77>;
gpio-config-reg = <0x801208>;
ep-reset-reg = <0x801210>;
ep-reset-gpio-mask = <0xf>;
dump-regs = <0x801330 0x801350 0x801370>;
version-reg = <0x800000>;
force-i2c-setting;
};
};

17
bindings/soc/qcom/qcom,crypto.txt Normal file
View File

@@ -0,0 +1,17 @@
QTI Microdump Collector Driver
This driver registers for Hibernate Power Management ops
and notifys TZ on Hibernate exit.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,crypto"
= EXAMPLE
&soc {
crypto_node {
compatible = "qcom,crypto";
};
};

28
bindings/soc/qcom/qcom,power-state.txt Normal file
View File

@@ -0,0 +1,28 @@
* Qualcomm Technologies, Inc. Power State Driver
This binding describes the Qualcomm Technologies, Inc. Power State Driver. Power
State creates power_state device node for user space communication. User space
client can open device node for communication and driver accordingly handles the
request.
Required Properties:
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,power-state"
- subsys-name:
Usage: required
Value type: <string>
Description: subsystem names supported
- rproc-handle:
Usage: required
Description: phandle to subsys defined in subsys-name.
Example:
qcom,power-state {
compatible = "qcom,power-state";
qcom,subsys-name = "adsp", "modem";
qcom,rproc-handle = <&adsp_pas>, <&modem_pas>;
};

105
qcom/Makefile
View File

@@ -422,7 +422,13 @@ dtbo-$(CONFIG_ARCH_PARROT) += parrot-rumi-overlay.dtbo \
parrot-qrd-wcn6750-overlay.dtbo \
parrot-qrd-wcn6750-4gb-overlay.dtbo \
parrot-qrd-nopmi-overlay.dtbo \
parrot-qrd-pm8350b-overlay.dtbo
parrot-qrd-pm8350b-overlay.dtbo \
parrot-idp-wcn6755-amoled-rcm-overlay.dtbo \
parrot-idp-wcn6755-overlay.dtbo \
parrot-qrd-wcn6755-overlay.dtbo \
parrot-idp-wcn6755-pm8350b-overlay.dtbo \
parrot-idp-wcn6755-nopmi-overlay.dtbo
parrot-rumi-overlay.dtbo-base := parrot.dtb
parrot-atp-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
@@ -444,6 +450,11 @@ parrot-qrd-wcn6750-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb par
parrot-qrd-wcn6750-4gb-overlay.dtbo-base := parrot-4gb.dtb
parrot-qrd-nopmi-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-qrd-pm8350b-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-idp-wcn6755-amoled-rcm-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-idp-wcn6755-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-qrd-wcn6755-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-idp-wcn6755-pm8350b-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
parrot-idp-wcn6755-nopmi-overlay.dtbo-base := parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb
else
dtb-$(CONFIG_ARCH_PARROT) += parrot-rumi.dtb \
parrot-atp.dtb \
@@ -500,7 +511,27 @@ dtb-$(CONFIG_ARCH_PARROT) += parrot-rumi.dtb \
parrotp-sg-qrd.dtb \
parrotp-sg-qrd-wcn6750.dtb \
parrotp-sg-qrd-nopmi.dtb \
parrotp-sg-qrd-pm8350b.dtb
parrotp-sg-qrd-pm8350b.dtb \
parrot-idp-wcn6755-amoled-rcm.dtb \
parrot-idp-wcn6755.dtb \
parrot-qrd-wcn6755.dtb \
parrot-idp-wcn6755-pm8350b.dtb \
parrot-idp-wcn6755-nopmi.dtb \
parrot-sg-idp-wcn6755-nopmi.dtb \
parrot-sg-idp-wcn6755-amoled-rcm.dtb \
parrot-sg-qrd-wcn6755.dtb \
parrot-sg-idp-wcn6755.dtb \
parrot-sg-idp-wcn6755-pm8350b.dtb \
parrotp-sg-qrd-wcn6755.dtb \
parrotp-sg-idp-wcn6755-nopmi.dtb \
parrotp-sg-idp-wcn6755.dtb \
parrotp-sg-idp-wcn6755-pm8350b.dtb \
parrotp-sg-idp-wcn6755-amoled-rcm.dtb \
parrotp-idp-wcn6755-amoled-rcm.dtb \
parrotp-idp-wcn6755-pm8350b.dtb \
parrotp-idp-wcn6755-nopmi.dtb \
parrotp-idp-wcn6755.dtb \
parrotp-qrd-wcn6755.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
@@ -561,7 +592,6 @@ dtbo-$(CONFIG_ARCH_RAVELIN) += ravelin-rumi-overlay.dtbo \
ravelin-qrd-4gb-overlay.dtbo \
montague-rumi-overlay.dtbo \
montague-hsp-overlay.dtbo \
montague-talyn-overlay.dtbo \
montague-moselle-overlay.dtbo \
montague-rcm-overlay.dtbo \
montague-wsa-overlay.dtbo \
@@ -571,15 +601,14 @@ dtbo-$(CONFIG_ARCH_RAVELIN) += ravelin-rumi-overlay.dtbo \
montague-apache-overlay.dtbo
ravelin-rumi-overlay.dtbo-base := ravelin.dtb montague.dtb
ravelin-atp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb montague.dtb montaguep.dtb
ravelin-idp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb montague.dtb montaguep.dtb
ravelin-idp-wcn3988-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb
ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo-base := ravelin.dtb ravelinp.dtb montague.dtb montaguep.dtb
ravelin-qrd-overlay.dtbo-base := ravelin.dtb ravelinp.dtb montague.dtb montaguep.dtb
ravelin-qrd-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb montague.dtb montaguep.dtb
ravelin-atp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb montague.dtb montaguep.dtb
ravelin-idp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb montague.dtb montaguep.dtb
ravelin-idp-wcn3988-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb ravelin-sg.dtb ravelinp-sg.dtb
ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo-base := ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb montague.dtb montaguep.dtb
ravelin-qrd-overlay.dtbo-base := ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb montague.dtb montaguep.dtb
ravelin-qrd-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb ravelin-sg.dtb ravelinp-sg.dtb montague.dtb montaguep.dtb
montague-rumi-overlay.dtbo-base := montague.dtb montaguep.dtb
montague-hsp-overlay.dtbo-base := montague.dtb montaguep.dtb
montague-talyn-overlay.dtbo-base := montague-talyn.dtb montaguep.dtb
montague-moselle-overlay.dtbo-base := montague-4gb.dtb montaguep-4gb.dtb montague.dtb montaguep.dtb
montague-rcm-overlay.dtbo-base := montague.dtb montaguep.dtb
montague-wsa-overlay.dtbo-base := montague.dtb montaguep.dtb
@@ -601,9 +630,20 @@ dtb-$(CONFIG_ARCH_RAVELIN) += ravelin-rumi.dtb \
ravelinp-idp-wcn3950-amoled-rcm.dtb \
ravelinp-qrd.dtb \
ravelinp-qrd-4gb.dtb \
ravelin-sg-atp.dtb \
ravelin-sg-idp.dtb \
ravelin-sg-idp-wcn3950-amoled-rcm.dtb \
ravelin-sg-idp-wcn3988-4gb.dtb \
ravelin-sg-qrd.dtb \
ravelin-sg-qrd-4gb.dtb \
ravelinp-sg-atp.dtb \
ravelinp-sg-idp.dtb \
ravelinp-sg-idp-wcn3950-amoled-rcm.dtb \
ravelinp-sg-idp-wcn3988-4gb.dtb \
ravelinp-sg-qrd.dtb \
ravelinp-sg-qrd-4gb.dtb \
montague-rumi.dtb \
montague-hsp.dtb \
montague-talyn.dtb \
montague-moselle.dtb \
montague-rcm.dtb \
montaguep-rumi.dtb \
@@ -656,6 +696,7 @@ dtbo-$(CONFIG_ARCH_ANORAK) += anorak-rumi-overlay.dtbo \
anorak-idp-hmt-overlay.dtbo \
anorak-qxr-hmt-ufs-ref-overlay.dtbo \
anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo \
anorakp-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo \
anorak-qxr-hmt-overlay.dtbo \
anorak-idp-sd-overlay.dtbo \
anorak-idp-top-hmt-overlay.dtbo \
@@ -664,19 +705,20 @@ dtbo-$(CONFIG_ARCH_ANORAK) += anorak-rumi-overlay.dtbo \
anorak-idp-4kdisp-hmt-overlay.dtbo \
anorak-idp-hsp-nodisplay-overlay.dtbo
anorak-rumi-overlay.dtbo-base := anorak.dtb
anorak-idp-overlay.dtbo-base := anorak.dtb
anorak-qxr-overlay.dtbo-base := anorak.dtb
anorak-atp-overlay.dtbo-base := anorak.dtb
anorak-idp-hmt-overlay.dtbo-base := anorak.dtb
anorak-qxr-hmt-ufs-ref-overlay.dtbo-base := anorak.dtb
anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo-base := anorak.dtb
anorak-qxr-hmt-overlay.dtbo-base := anorak.dtb
anorak-idp-sd-overlay.dtbo-base := anorak.dtb
anorak-idp-top-hmt-overlay.dtbo-base := anorak.dtb
anorak-idp-top-hsp-overlay.dtbo-base := anorak.dtb
anorak-idp-4kdisp-hsp-overlay.dtbo-base := anorak.dtb
anorak-idp-4kdisp-hmt-overlay.dtbo-base := anorak.dtb
anorak-idp-hsp-nodisplay-overlay.dtbo-base := anorak.dtb
anorak-idp-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-qxr-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-atp-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-hmt-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-qxr-hmt-ufs-ref-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorakp-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-qxr-hmt-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-sd-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-top-hmt-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-top-hsp-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-4kdisp-hsp-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-4kdisp-hmt-overlay.dtbo-base := anorak.dtb anorakp.dtb
anorak-idp-hsp-nodisplay-overlay.dtbo-base := anorak.dtb anorakp.dtb
else
dtb-$(CONFIG_ARCH_ANORAK) += anorak-rumi.dtb \
anorak-idp.dtb \
@@ -691,7 +733,20 @@ dtb-$(CONFIG_ARCH_ANORAK) += anorak-rumi.dtb \
anorak-idp-top-hsp.dtb \
anorak-idp-4kdisp-hsp.dtb \
anorak-idp-4kdisp-hmt.dtb \
anorak-idp-hsp-nodisplay.dtb
anorak-idp-hsp-nodisplay.dtb \
anorakp-idp.dtb \
anorakp-qxr.dtb \
anorakp-atp.dtb \
anorakp-idp-hmt.dtb \
anorakp-qxr-hmt-ufs-ref.dtb \
anorakp-qxr-4kdisp-hmt-ufs-ref.dtb \
anorakp-qxr-hmt.dtb \
anorakp-idp-sd.dtb \
anorakp-idp-top-hmt.dtb \
anorakp-idp-top-hsp.dtb \
anorakp-idp-4kdisp-hsp.dtb \
anorakp-idp-4kdisp-hmt.dtb \
anorakp-idp-hsp-nodisplay.dtb
endif
ifeq ($(CONFIG_ARCH_LAHAINA), y)

2
qcom/anorak-atp-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak ATP";
compatible = "qcom,anorak-atp", "qcom,anorak", "qcom,atp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10021 0x0>;
};

33
qcom/anorak-atp.dtsi
View File

@@ -166,34 +166,6 @@
status = "disabled";
};
&cnss_pins {
cnss_host_sol_default: cnss_host_sol_default {
mux {
pins = "gpio124";
function = "gpio";
};
config {
pins = "gpio124";
drive-strength = <4>;
bias-pull-down;
};
};
cnss_dev_sol_default: cnss_dev_sol_default {
mux {
pins = "gpio123";
function = "gpio";
};
config {
pins = "gpio123";
drive-strength = <4>;
bias-pull-down;
};
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
@@ -201,13 +173,10 @@
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 120 0>;
wlan-host-sol-gpio = <&tlmm 124 0>;
wlan-dev-sol-gpio = <&tlmm 123 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sol_default";
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
pinctrl-2 = <&cnss_host_sol_default &cnss_dev_sol_default>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;

606
qcom/anorak-gpu.dtsi
View File

@@ -37,8 +37,6 @@
qcom,chipid = <0x43050b00>;
qcom,initial-pwrlevel = <9>;
qcom,no-nap;
qcom,min-access-length = <32>;
@@ -77,130 +75,558 @@
};
/* Power levels */
qcom,gpu-pwrlevels {
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
compatible = "qcom,gpu-pwrlevel-bins";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <690000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <9>;
qcom,acd-level = <0xa82c5ffd>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <690000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <456000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <4>;
qcom,bus-max = <9>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <317000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0xe02a5ffd>;
};
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,speed-bin = <146>;
qcom,initial-pwrlevel = <9>;
qcom,acd-level = <0x882e5ffd>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <690000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <456000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <4>;
qcom,bus-max = <9>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <317000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0xe02a5ffd>;
};
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,speed-bin = <167>;
qcom,initial-pwrlevel = <12>;
qcom,acd-level = <0x882e5ffd>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <788000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <750000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <730000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <690000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <456000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <4>;
qcom,bus-max = <9>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <317000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0xe02a5ffd>;
};
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,gpu-pwrlevels-3 {
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,speed-bin = <168>;
qcom,initial-pwrlevel = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <690000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <456000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <9>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,bus-freq = <7>;
qcom,bus-min = <4>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <317000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <456000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,acd-level = <0xe02a5ffd>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <4>;
qcom,bus-max = <9>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <317000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <0xc0295ffd>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0xe02a5ffd>;
};
};
};

2
qcom/anorak-idp-4kdisp-hmt-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HMT";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x6>;
};

2
qcom/anorak-idp-4kdisp-hsp-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HSP";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x5>;
};

2
qcom/anorak-idp-hmt-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP HMT";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x1>;
};

2
qcom/anorak-idp-hsp-nodisplay-overlay.dts
View File

@@ -6,7 +6,7 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP HSP with no display";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x7>;
};

2
qcom/anorak-idp-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x0>;
};

2
qcom/anorak-idp-sd-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP Single Display";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x2>;
};

2
qcom/anorak-idp-top-hmt-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP Topanga Hamilton";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x3>;
};

2
qcom/anorak-idp-top-hsp-overlay.dts
View File

@@ -6,7 +6,7 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak IDP Topanga with EDP display + HSP";
compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10022 0x4>;
};

2
qcom/anorak-pcie.dtsi
View File

@@ -665,6 +665,8 @@
qcom,l1-2-th-value = <150>;
qcom,pcie-phy-ver = <114>;
qcom,phy-aux-clk-config1-offset = <0x1450>;
qcom,phy-pll-clk-enable1-offset = <0x1048>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;

7
qcom/anorak-qxr-4kdisp-hmt-ufs-ref.dtsi
View File

@@ -1 +1,8 @@
#include "anorak-qxr-hmt-ufs-ref.dtsi"
&k09973 {
ipd,SW_event = <0 1 1 0>;
ipd,SMR_setting = <0>;
ipd,Device_type = <2>;
};

2
qcom/anorak-qxr-hmt-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak QXR HMT";
compatible = "qcom,anorak-qxr", "qcom,anorak";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10026 0x1>;
};

2
qcom/anorak-qxr-hmt-ufs-ref-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak QXR HMT UFS REF";
compatible = "qcom,anorak-qxr", "qcom,anorak";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10126 0x2>;
};

2
qcom/anorak-qxr-overlay.dts
View File

@@ -6,6 +6,6 @@
/ {
model = "Qualcomm Technologies, Inc. Anorak QXR";
compatible = "qcom,anorak-qxr", "qcom,anorak";
qcom,msm-id = <549 0x10000>;
qcom,msm-id = <549 0x10000>,<649 0x10000>;
qcom,board-id = <0x10026 0x0>;
};

2
qcom/anorak-qxr.dtsi
View File

@@ -357,6 +357,8 @@
&itof_level {
enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <4300000>;
regulator-max-microvolt = <4300000>;
status = "ok";
};

1
qcom/anorak.dtsi
View File

@@ -554,7 +554,6 @@
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";

10
qcom/anorakp-atp.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP ATP";
compatible = "qcom,anorakp-atp", "qcom,anorakp", "qcom,atp";
qcom,board-id = <0x10021 0x0>;
};

1
qcom/anorakp-atp.dtsi Normal file
View File

@@ -0,0 +1 @@
#include "anorak-atp.dtsi"

10
qcom/anorakp-idp-4kdisp-hmt.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-4kdisp-hmt.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP 4K display + HMT";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x6>;
};

1
qcom/anorakp-idp-4kdisp-hmt.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-4kdisp-hmt.dtsi"

10
qcom/anorakp-idp-4kdisp-hsp.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-4kdisp-hsp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP 4K display + HSP";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x5>;
};

1
qcom/anorakp-idp-4kdisp-hsp.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-4kdisp-hsp.dtsi"

10
qcom/anorakp-idp-hmt.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-hmt.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP HMT";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x1>;
};

1
qcom/anorakp-idp-hmt.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-hmt.dtsi"

10
qcom/anorakp-idp-hsp-nodisplay.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-hsp-nodisplay.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP HSP with no display";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x7>;
};

1
qcom/anorakp-idp-hsp-nodisplay.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-hsp-nodisplay.dtsi"

10
qcom/anorakp-idp-sd.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-sd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP Single Display";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x2>;
};

1
qcom/anorakp-idp-sd.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-sd.dtsi"

10
qcom/anorakp-idp-top-hmt.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-top-hmt.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP Topanga Hamilton";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x3>;
};

1
qcom/anorakp-idp-top-hmt.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-top-hmt.dtsi"

10
qcom/anorakp-idp-top-hsp.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp-top-hsp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP Topanga with EDP display + HSP";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x4>;
};

1
qcom/anorakp-idp-top-hsp.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp-top-hsp.dtsi"

10
qcom/anorakp-idp.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP IDP";
compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
qcom,board-id = <0x10022 0x0>;
};

1
qcom/anorakp-idp.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-idp.dtsi"

11
qcom/anorakp-qxr-4kdisp-hmt-ufs-ref-overlay.dts Normal file
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@@ -0,0 +1,11 @@
/dts-v1/;
/plugin/;
#include "anorakp-qxr-4kdisp-hmt-ufs-ref.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP QXR HMT UFS REF + 4K Display";
compatible = "qcom,anorakp-qxr", "qcom,anorakp";
qcom,msm-id = <649 0x10000>;
qcom,board-id = <0x10126 0x3>;
};

10
qcom/anorakp-qxr-4kdisp-hmt-ufs-ref.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-qxr-4kdisp-hmt-ufs-ref.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP QXR HMT UFS REF + 4K Display";
compatible = "qcom,anorakp-qxr", "qcom,anorakp";
qcom,board-id = <0x10126 0x3>;
};

1
qcom/anorakp-qxr-4kdisp-hmt-ufs-ref.dtsi Normal file
View File

@@ -0,0 +1 @@
#include "anorak-qxr-4kdisp-hmt-ufs-ref.dtsi"

10
qcom/anorakp-qxr-hmt-ufs-ref.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-qxr-hmt-ufs-ref.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP QXR HMT UFS REF";
compatible = "qcom,anorakp-qxr", "qcom,anorakp";
qcom,board-id = <0x10126 0x2>;
};

1
qcom/anorakp-qxr-hmt-ufs-ref.dtsi Normal file
View File

@@ -0,0 +1 @@
#include "anorak-qxr-hmt-ufs-ref.dtsi"

10
qcom/anorakp-qxr-hmt.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-qxr-hmt.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP QXR HMT";
compatible = "qcom,anorakp-qxr", "qcom,anorakp";
qcom,board-id = <0x10026 0x1>;
};

1
qcom/anorakp-qxr-hmt.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-qxr-hmt.dtsi"

10
qcom/anorakp-qxr.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "anorakp.dtsi"
#include "anorakp-qxr.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP QXR";
compatible = "qcom,anorakp-qxr", "qcom,anorakp";
qcom,board-id = <0x10026 0x0>;
};

1
qcom/anorakp-qxr.dtsi Normal file
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@@ -0,0 +1 @@
#include "anorak-qxr.dtsi"

9
qcom/anorakp.dts Normal file
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@@ -0,0 +1,9 @@
/dts-v1/;
#include "anorakp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP SoC";
compatible = "qcom,anorakp";
qcom,board-id = <0 0>;
};

7
qcom/anorakp.dtsi Normal file
View File

@@ -0,0 +1,7 @@
#include "anorak.dtsi"
/ {
model = "Qualcomm Technologies, Inc. AnorakP";
compatible = "qcom,anorakp";
qcom,msm-id = <649 0x10000>;
};

7
qcom/montague-adrastea-overlay.dts
View File

@@ -9,3 +9,10 @@
qcom,msm-id = <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x10022 0x0>;
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

2
qcom/montague-apache-overlay.dts
View File

@@ -1,7 +1,7 @@
/dts-v1/;
/plugin/;
#include "montague-apache.dtsi"
#include "montague-talyn.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Montague Apache IDP";

2
qcom/montague-apache.dts
View File

@@ -1,7 +1,7 @@
/dts-v1/;
#include "montague.dtsi"
#include "montague-apache.dtsi"
#include "montague-talyn.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Montague Apache IDP";

8
qcom/montague-hsp-overlay.dts
View File

@@ -16,3 +16,11 @@
reg = <0x0 0x82a00000 0x0 0x0>;
};
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

160
qcom/montague-idp-qps615.dtsi
View File

@@ -1 +1,159 @@
#include "ravelin-idp.dtsi"
#include "montague-hsp.dtsi"
&qupv3_se0_i2c {
status = "ok";
pcie0_i2c_ctrl: pcie0_i2c_ctrl {
compatible = "qcom,pcie-i2c-ntn3";
rc-index = <0x0>;
reg = <0x77>;
gpio-config-reg = <0x801208>;
ep-reset-reg = <0x801210>;
ep-reset-gpio-mask = <0xc>;
version-reg = <0x800000>;
dump-regs = <0x801330 0x801350 0x801370>;
reg_update = <0x82c030 0x1
0x828000 0x3
0x82bd00 0x8
0x82c030 0x2
0x828000 0x3
0x82bd00 0x8
0x82c030 0x8
0x828000 0x1
0x82bd00 0x8
0x82c01c 0x10
0x82c030 0xf
0x828000 0xf
0x82b268 0x2>;
/*FOM for preset caluclation*/
switch_reg_update = <0x82c02c 0x00000007
0x824a10 0x00000001
0x82c030 0x00000008
0x828000 0x00000001
0x82b074 0x00000020
0x82b2bc 0x00000001>;
};
};
&pcie0 {
pcie-i2c-phandle = <&qupv3_se0_i2c>;
qcom,boot-option = <0x2>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>,
<0x208 &apps_smmu 0x1404 0x1>,
<0x210 &apps_smmu 0x1405 0x1>,
<0x218 &apps_smmu 0x1406 0x1>,
<0x300 &apps_smmu 0x1407 0x1>,
<0x400 &apps_smmu 0x1410 0x1>,
<0x500 &apps_smmu 0x1411 0x1>,
<0x501 &apps_smmu 0x1412 0x1>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xca 0x0
0x01b8 0x18 0x0
0x01b4 0xa2 0x0
0x0050 0x07 0x0
0x0010 0x01 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0ee4 0x20 0x0
0x0e84 0x75 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0xbf 0x0
0x1168 0x3f 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x1194 0x38 0x0
0x10d8 0x0f 0x0
0x0e3c 0x12 0x0
0x0e40 0x01 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x10f4 0x07 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0624 0x40 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
/* BDF 1.0.0 */
pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
reg = <0 0 0 0 0>;
/* BDF 2.1.0 */
pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
reg = <0x800 0x0 0x0 0x0 0x0>;
};
/* BDF 2.2.0 */
pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
reg = <0x1000 0x0 0x0 0x0 0x0>;
};
/* BDF 2.3.0 */
pcie0_bus2_dev3_fn0: pcie0_bus2_dev3_fn0 {
reg = <0x1800 0x0 0x0 0x0 0x0>;
};
};
};

8
qcom/montague-moselle-overlay.dts
View File

@@ -10,3 +10,11 @@
qcom,board-id = <0x10022 3>;
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

8
qcom/montague-rcm-overlay.dts
View File

@@ -10,3 +10,11 @@
qcom,board-id = <0x10022 0x5>;
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

11
qcom/montague-talyn-overlay.dts
View File

@@ -1,11 +0,0 @@
/dts-v1/;
/plugin/;
#include "montague-talyn.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Apache wigig IDP";
compatible = "qcom,montague-idp", "qcom,montague", "qcom,idp";
qcom,msm-id = <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x10022 0x08>;
};

11
qcom/montague-talyn.dts
View File

@@ -1,11 +0,0 @@
/dts-v1/;
#include "montague.dtsi"
#include "montague-talyn.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Apache wigig IDP";
compatible = "qcom,montague-idp", "qcom,montague", "qcom,idp";
qcom,board-id = <0 0>;
};

8
qcom/montague-wsa-overlay.dts
View File

@@ -9,3 +9,11 @@
qcom,msm-id = <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x10022 0x7>;
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

8
qcom/montague-wsd-overlay.dts
View File

@@ -9,3 +9,11 @@
qcom,msm-id = <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x10022 0x6>;
};
&pcie0 {
qcom,config-recovery;
qcom,drv-supported;
};

15
qcom/montague.dtsi
View File

@@ -17,6 +17,13 @@
};
&soc {
st54spi_gpio {
status = "ok";
compatible = "st,st54spi_gpio";
/* gpio used as SE_nRESET */
gpio-power_nreset = <&tlmm 48 0x00>;
};
mhi_qrtr_cnss {
compatible = "qcom,qrtr-mhi";
qcom,dev-id = <0x1103>;
@@ -24,3 +31,11 @@
qcom,low-latency;
};
};
&pcie0 {
/delete-property/ qcom,config-recovery;
/delete-property/ qcom,drv-supported;
};

2
qcom/montaguep-apache.dts
View File

@@ -1,7 +1,7 @@
/dts-v1/;
#include "montaguep.dtsi"
#include "montaguep-apache.dtsi"
#include "montague-talyn.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Montague Apache IDP";

1
qcom/montaguep-apache.dtsi
View File

@@ -1 +0,0 @@
#include "ravelinp-idp.dtsi"

6
qcom/neo-pcie.dtsi
View File

@@ -128,7 +128,7 @@
qcom,config-recovery;
qcom,target-link-speed = <0x2>;
qcom,pcie-phy-ver = <104>;
qcom,pcie-phy-ver = <107>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
@@ -244,6 +244,7 @@
0x0694 0x00 0x0
0x03d0 0x8c 0x0
0x0368 0x17 0x0
0x0370 0x2e 0x0
0x1424 0x01 0x0
0x1428 0x01 0x0
0x0200 0x00 0x0
@@ -419,7 +420,7 @@
qcom,num-parf-testbus-sel = <0xb9>;
qcom,config-recovery;
qcom,pcie-phy-ver = <104>;
qcom,pcie-phy-ver = <107>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
@@ -535,6 +536,7 @@
0x0694 0x00 0x0
0x03d0 0x8c 0x0
0x0368 0x17 0x0
0x0370 0x2e 0x0
0x1424 0x01 0x0
0x1428 0x01 0x0
0x0200 0x00 0x0

10
qcom/neo.dtsi
View File

@@ -1030,6 +1030,10 @@
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
crypto_node {
compatible = "qcom,crypto";
};
sdhc_1: sdhci@7C4000 {
status = "disabled";
@@ -1765,6 +1769,12 @@
ddr-freq-update;
};
qcom,power-state {
compatible = "qcom,power-state";
qcom,subsys-name = "lpass", "cdsp";
qcom,rproc-handle = <&adsp_pas>, <&cdsp_pas>;
};
sys-pm-vx@c320000 {
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-neo";
reg = <0xc320000 0x0400>;

31
qcom/neo_la.dtsi
View File

@@ -240,6 +240,37 @@
};
};
bwprof: qcom,bwprof-ddr@19090000 {
compatible = "qcom,bwprof";
#address-cells = <1>;
#size-cells = <1>;
qcom,bus-width = <4>;
ranges;
reg = <0x190BA050 0x10>;
reg-names = "mem-freq";
bwprof_0: qcom,bwprof0@19092000 {
compatible = "qcom,bwprof-mon";
reg = <0x19092000 0x1000>;
reg-names = "base";
client = "total";
};
bwprof_1: qcom,bwprof1@19093000 {
compatible = "qcom,bwprof-mon";
reg = <0x19093000 0x1000>;
reg-names = "base";
client = "cpu";
};
bwprof_2: qcom,bwprof2@19094000 {
compatible = "qcom,bwprof-mon";
reg = <0x19094000 0x1000>;
reg-names = "base";
client = "gpu";
};
};
bluetooth: bt_wcn6x5x {
compatible = "qcom,kiwi";
pinctrl-names = "default";

3
qcom/parrot-atp-overlay.dts
View File

@@ -8,6 +8,7 @@
model = "Qualcomm Technologies, Inc. Parrot ATP";
compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <33 0>;
};

2
qcom/parrot-idp-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <34 0x600>;
};

3
qcom/parrot-idp-nopmi-overlay.dts
View File

@@ -8,7 +8,8 @@
model = "Qualcomm Technologies, Inc. Parrot IDP";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 0>;
qcom,pmic-id-size = <9>;
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;

3
qcom/parrot-idp-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot IDP";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 0>;
};

3
qcom/parrot-idp-pm8350b-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot IDP";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 0>;
};

2
qcom/parrot-idp-wcn3990-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR + WCN3990";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <34 0x601>;
};

2
qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP 4GB DDR + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <34 0x603>;
};

3
qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 3>;
};

3
qcom/parrot-idp-wcn3990-overlay.dts
View File

@@ -8,6 +8,7 @@
model = "Qualcomm Technologies, Inc. Parrot IDP + WCN3990";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 1>;
};

2
qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <34 0x604>;
};

2
qcom/parrot-idp-wcn6750-amoled-overlay.dts
View File

@@ -9,6 +9,6 @@
model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>;
qcom,board-id = <34 4>;
};

2
qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <34 0x602>;
};

3
qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 2>;
};

15
qcom/parrot-idp-wcn6755-amoled-rcm-overlay.dts Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
#include "parrot-idp-wcn6750-amoled-rcm.dtsi"
#include "parrot-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 6>;
};

12
qcom/parrot-idp-wcn6755-amoled-rcm.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
#include "parrot.dtsi"
#include "parrot-wcn6755.dtsi"
#include "parrot-idp-wcn6750-amoled-rcm.dtsi"
#include "parrot-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP + AMOLED + RCM";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,board-id = <34 6>;
};

16
qcom/parrot-idp-wcn6755-nopmi-overlay.dts Normal file
View File

@@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 5>;
qcom,pmic-id-size = <9>;
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
};

13
qcom/parrot-idp-wcn6755-nopmi.dts Normal file
View File

@@ -0,0 +1,13 @@
/dts-v1/;
#include "parrot.dtsi"
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,board-id = <34 5>;
qcom,pmic-id-size = <9>;
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
};

15
qcom/parrot-idp-wcn6755-overlay.dts Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
#include "parrot-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 5>;
};

15
qcom/parrot-idp-wcn6755-pm8350b-overlay.dts Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
#include "parrot-idp-pm8350b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <34 5>;
};

12
qcom/parrot-idp-wcn6755-pm8350b.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
#include "parrot.dtsi"
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
#include "parrot-idp-pm8350b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,board-id = <34 5>;
};

12
qcom/parrot-idp-wcn6755.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
#include "parrot.dtsi"
#include "parrot-wcn6755.dtsi"
#include "parrot-idp.dtsi"
#include "parrot-idp-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP";
compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
qcom,board-id = <34 5>;
};

2
qcom/parrot-qrd-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot QRD 4GB DDR";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <0x1000B 0x600>;
};

3
qcom/parrot-qrd-nopmi-overlay.dts
View File

@@ -8,7 +8,8 @@
model = "Qualcomm Technologies, Inc. Parrot QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <0x1000B 0>;
qcom,pmic-id-size = <9>;
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;

3
qcom/parrot-qrd-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <0x1000B 0>;
};

3
qcom/parrot-qrd-pm8350b-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <0x1000B 0>;
};

2
qcom/parrot-qrd-wcn6750-4gb-overlay.dts
View File

@@ -8,6 +8,6 @@
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD 4GB DDR";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>;
qcom,msm-id = <537 0x10000>, <663 0x10000>;
qcom,board-id = <0x1000B 0x601>;
};

3
qcom/parrot-qrd-wcn6750-overlay.dts
View File

@@ -9,6 +9,7 @@
model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>;
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <0x1000B 1>;
};

15
qcom/parrot-qrd-wcn6755-overlay.dts Normal file
View File

@@ -0,0 +1,15 @@
/dts-v1/;
/plugin/;
#include "parrot-wcn6755.dtsi"
#include "parrot-qrd-wcn6750.dtsi"
#include "parrot-qrd-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
<633 0x10000>, <634 0x10000>, <638 0x10000>,
<663 0x10000>;
qcom,board-id = <0x1000B 2>;
};

12
qcom/parrot-qrd-wcn6755.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
#include "parrot.dtsi"
#include "parrot-wcn6755.dtsi"
#include "parrot-qrd-wcn6750.dtsi"
#include "parrot-qrd-pm7250b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Parrot WCN6755 QRD";
compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd";
qcom,board-id = <0x1000B 2>;
};

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