mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
ARM: dts: msm: add initial dt files to support Diwali VM
Add initial DT files to support VM for Diwali. Change-Id: Iffa95cf948facef6a1c0b38468e69aa370ffe672
This commit is contained in:
Mukesh Ojha
@@ -288,6 +288,13 @@ dtb-$(CONFIG_ARCH_QTI_VM) += waipio-vm-mtp.dtb \
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endif
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endif
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ifeq ($(CONFIG_ARCH_DIWALI), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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dtb-$(CONFIG_ARCH_QTI_VM) += \
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diwali-vm-rumi.dtb
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endif
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endif
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always-y := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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10
qcom/diwali-vm-rumi.dts
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10
qcom/diwali-vm-rumi.dts
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@@ -0,0 +1,10 @@
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/dts-v1/;
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#include "diwali-vm.dtsi"
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#include "diwali-vm-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Diwali SVM RUMI";
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compatible = "qcom,diwali-rumi", "qcom,diwali", "qcom,rumi";
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qcom,board-id = <15 0>;
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};
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3
qcom/diwali-vm-rumi.dtsi
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3
qcom/diwali-vm-rumi.dtsi
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@@ -0,0 +1,3 @@
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&arch_timer {
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clock-frequency = <500000>;
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};
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226
qcom/diwali-vm.dtsi
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226
qcom/diwali-vm.dtsi
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@@ -0,0 +1,226 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <506 0x10000>;
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interrupt-parent = <&vgic>;
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qcom,mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "consumer";
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qcom,vmid = <45>;
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};
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qcom,mem-buf-msgq {
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compatible = "qcom,mem-buf-msgq";
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};
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chosen {
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bootargs = "cpuidle.off=1 console=hvc0 nokaslr log_buf_len=256K root=/dev/ram rw init=/init loglevel=8";
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <369>;
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exit-latency-us = <1502>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_PWR_DWN: d4 { /* C4+D4 */
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compatible = "arm,idle-state";
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idle-state-name = "l3-pc";
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entry-latency-us = <584>;
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exit-latency-us = <2332>;
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min-residency-us = <6118>;
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arm,psci-suspend-param = <0x40000044>;
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local-timer-stop;
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};
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};
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qrtr-gunyah {
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compatible = "qcom,qrtr-gunyah";
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gunyah-label = <3>;
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "Qualcomm";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
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0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
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0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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base-address = <0x0 0xe0b00000>;
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size-min = <0x0 0x4c00000>; /* 76 MB */
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};
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segments {
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ramdisk = <2>; /* 8MB */
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};
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vcpus {
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config = "/cpus";
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affinity = "static";
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affinity-map = <0x5 0x6>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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virtio-mmio@0 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x1>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x0>;
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memory {
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qcom,label = <0x11>;
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#address-cells = <0x2>;
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base = <0x0 0xFFEFC000>;
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};
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};
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swiotlb-shm {
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vdevice-type = "shm";
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generate = "/swiotlb";
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push-compatible = "swiotlb";
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peer-default;
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dma_base = <0x0 0x4000>;
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memory {
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qcom,label = <0x12>;
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#address-cells = <0x2>;
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base = <0x0 0xFFF00000>;
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};
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};
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mem-buf-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/membuf-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000001>;
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};
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display-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/display-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000002>;
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};
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qrtr-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/qrtr-shm";
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push-compatible = "qcom,qrtr-gunyah-gen";
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peer-default;
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memory {
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qcom,label = <0x3>;
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allocate-base;
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};
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};
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};
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};
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x100000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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};
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