mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
ARM: dts: msm: Add PCIe configuration for anorak
This change enables PCIe controller and add related configuration for the anorak Target. Change-Id: I4eb4fefbe6e7009f7e19f0ae6b080f73be2f0aaa
This commit is contained in:
Krishna Chaitanya Chundru
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
72a1da1fff
commit
9d12f06d42
816
qcom/anorak-pcie.dtsi
Normal file
816
qcom/anorak-pcie.dtsi
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@@ -0,0 +1,816 @@
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#include <dt-bindings/clock/qcom,gcc-anorak.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p8-supply = <&L1E>;
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vreg-0p9-supply = <&L2E>;
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vreg-qref-supply = <&L2D>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 15000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 45800>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-qref-voltage-level = <880000 880000 600>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
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<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk",
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"pcie_aggre_noc_0_axi_clk",
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"pcie_aggre_noc_sf_axi_clk",
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"pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_0_pipe_div2_clk",
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"pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <150000000>,
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<0>, <0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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// qcom,smmu-sid-base = <0x2c80>;
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// iommu-map = <0x0 &apps_smmu 0x2c80 0x1>,
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// <0x100 &apps_smmu 0x2c81 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-supported;
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,config-recovery;
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qcom,pcie-phy-ver = <106>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x0048 0x90 0x0
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0x0058 0x0f 0x0
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0x0074 0x06 0x0
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0x0078 0x06 0x0
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0x007c 0x16 0x0
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0x0080 0x16 0x0
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0x0084 0x36 0x0
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0x0088 0x36 0x0
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0x0094 0x04 0x0
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0x00a4 0x42 0x0
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0x00ac 0x0a 0x0
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0x00b0 0x1a 0x0
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0x00b4 0x14 0x0
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0x00b8 0x34 0x0
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0x00bc 0x82 0x0
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0x00c4 0x68 0x0
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0x00cc 0x55 0x0
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0x00d0 0x55 0x0
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0x00d4 0x03 0x0
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0x00d8 0xab 0x0
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0x00dc 0xaa 0x0
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0x00e0 0x02 0x0
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0x010c 0x02 0x0
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0x0110 0x24 0x0
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0x0118 0xb4 0x0
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0x011c 0x03 0x0
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0x0154 0x34 0x0
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0x0158 0x01 0x0
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0x016c 0x08 0x0
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0x01ac 0xb9 0x0
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0x01b0 0x1e 0x0
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0x01b4 0x94 0x0
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0x01b8 0x18 0x0
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0x01bc 0x11 0x0
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0x0ee4 0x02 0x0
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0x16e4 0x04 0x0
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0x1684 0xd5 0x0
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0x0e84 0xd5 0x0
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0x1690 0x3f 0x0
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0x0e90 0x3f 0x0
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0x115c 0x7f 0x0
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0x1160 0xff 0x0
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0x1164 0x7f 0x0
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0x1168 0x34 0x0
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0x116c 0xd8 0x0
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0x1170 0xdc 0x0
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0x1174 0xdc 0x0
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0x1178 0x5c 0x0
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0x117c 0x34 0x0
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0x1180 0xa6 0x0
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0x195c 0x7f 0x0
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0x1960 0xff 0x0
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0x1964 0x7f 0x0
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0x1968 0x34 0x0
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0x196c 0xd8 0x0
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0x1970 0xdc 0x0
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0x1974 0xdc 0x0
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0x1978 0x5c 0x0
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0x197c 0x34 0x0
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0x1980 0xa6 0x0
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0x10cc 0xf0 0x0
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0x18cc 0xf0 0x0
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0x10d8 0x0f 0x0
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0x18d8 0x0f 0x0
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0x10dc 0x00 0x0
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0x18dc 0x00 0x0
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0x11a4 0x38 0x0
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0x19a4 0x38 0x0
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0x0e3c 0x1d 0x0
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0x163c 0x1d 0x0
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0x0e40 0x0c 0x0
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0x1640 0x0c 0x0
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0x1190 0x34 0x0
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0x1990 0x34 0x0
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0x104c 0x08 0x0
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0x184c 0x08 0x0
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0x1050 0x08 0x0
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0x1850 0x08 0x0
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0x02dc 0x05 0x0
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0x0388 0x77 0x0
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0x0398 0x0b 0x0
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0x03e0 0x0f 0x0
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0x060c 0x1d 0x0
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0x0614 0x07 0x0
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0x0620 0xc1 0x0
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0x0694 0x00 0x0
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0x0200 0x00 0x0
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0x0244 0x03 0x0>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@0x17210040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17210040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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};
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pcie1: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c08000 0x3000>,
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<0x01c0e000 0x2000>,
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<0x64000000 0xf1d>,
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<0x64000F20 0xa8>,
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<0x64001000 0x1000>,
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<0x64100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <1>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,
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<0x02000000 0x0 0x64300000 0x64300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie1>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie1_msi>;
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perst-gpio = <&tlmm 141 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 143 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie1_perst_default
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&pcie1_clkreq_default
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&pcie1_wake_default>;
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pinctrl-1 = <&pcie1_perst_default
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&pcie1_clkreq_sleep
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&pcie1_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
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vreg-1p8-supply = <&L1E>;
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vreg-0p9-supply = <&L2E>;
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vreg-qref-supply = <&L2D>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 25800>;
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qcom,vreg-0p9-voltage-level = <880000 880000 186000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
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qcom,vreg-qref-voltage-level = <880000 880000 600>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
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<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
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<&pcie_1_pipe_clk>;
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clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
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"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
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"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
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"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
|
||||
"pcie_phy_refgen_clk",
|
||||
"pcie_ddrss_sf_tbu_clk",
|
||||
"pcie_aggre_noc_0_axi_clk", "pcie_aggre_noc_sf_axi_clk",
|
||||
"pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_1_pipe_div2_clk",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <0>, <150000000>, <0>,
|
||||
<0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_1_BCR>,
|
||||
<&gcc GCC_PCIE_1_PHY_BCR>;
|
||||
reset-names = "pcie_1_core_reset",
|
||||
"pcie_1_phy_reset";
|
||||
|
||||
dma-coherent;
|
||||
//qcom,smmu-sid-base = <0x2d00>;
|
||||
//iommu-map = <0x0 &apps_smmu 0x2d00 0x1>,
|
||||
// <0x100 &apps_smmu 0x2d01 0x1>;
|
||||
|
||||
qcom,boot-option = <0x1>;
|
||||
qcom,drv-supported;
|
||||
qcom,drv-l1ss-timeout-us = <5000>;
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,slv-addr-space-size = <0x20000000>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
qcom,l1-2-th-scale = <2>;
|
||||
qcom,l1-2-th-value = <150>;
|
||||
|
||||
qcom,pcie-phy-ver = <106>;
|
||||
qcom,phy-status-offset = <0x214>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x240>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x001c 0x31 0x0
|
||||
0x0020 0x01 0x0
|
||||
0x0024 0xde 0x0
|
||||
0x0028 0x07 0x0
|
||||
0x0030 0x4c 0x0
|
||||
0x0034 0x06 0x0
|
||||
0x0048 0x90 0x0
|
||||
0x0058 0x0f 0x0
|
||||
0x0074 0x06 0x0
|
||||
0x0078 0x06 0x0
|
||||
0x007c 0x16 0x0
|
||||
0x0080 0x16 0x0
|
||||
0x0084 0x36 0x0
|
||||
0x0088 0x36 0x0
|
||||
0x0094 0x04 0x0
|
||||
0x00a4 0x42 0x0
|
||||
0x00ac 0x0a 0x0
|
||||
0x00b0 0x1a 0x0
|
||||
0x00b4 0x14 0x0
|
||||
0x00b8 0x34 0x0
|
||||
0x00bc 0x82 0x0
|
||||
0x00c4 0x68 0x0
|
||||
0x00cc 0x55 0x0
|
||||
0x00d0 0x55 0x0
|
||||
0x00d4 0x03 0x0
|
||||
0x00d8 0xab 0x0
|
||||
0x00dc 0xaa 0x0
|
||||
0x00e0 0x02 0x0
|
||||
0x010c 0x02 0x0
|
||||
0x0110 0x24 0x0
|
||||
0x0118 0xb4 0x0
|
||||
0x011c 0x03 0x0
|
||||
0x0154 0x34 0x0
|
||||
0x0158 0x01 0x0
|
||||
0x016c 0x08 0x0
|
||||
0x01ac 0xb9 0x0
|
||||
0x01b0 0x1e 0x0
|
||||
0x01b4 0x94 0x0
|
||||
0x01b8 0x18 0x0
|
||||
0x01bc 0x11 0x0
|
||||
0x0ee4 0x02 0x0
|
||||
0x16e4 0x04 0x0
|
||||
0x1684 0xd5 0x0
|
||||
0x0e84 0xd5 0x0
|
||||
0x1690 0x3f 0x0
|
||||
0x0e90 0x3f 0x0
|
||||
0x115c 0x7f 0x0
|
||||
0x1160 0xff 0x0
|
||||
0x1164 0x7f 0x0
|
||||
0x1168 0x34 0x0
|
||||
0x116c 0xd8 0x0
|
||||
0x1170 0xdc 0x0
|
||||
0x1174 0xdc 0x0
|
||||
0x1178 0x5c 0x0
|
||||
0x117c 0x34 0x0
|
||||
0x1180 0xa6 0x0
|
||||
0x195c 0x7f 0x0
|
||||
0x1960 0xff 0x0
|
||||
0x1964 0x7f 0x0
|
||||
0x1968 0x34 0x0
|
||||
0x196c 0xd8 0x0
|
||||
0x1970 0xdc 0x0
|
||||
0x1974 0xdc 0x0
|
||||
0x1978 0x5c 0x0
|
||||
0x197c 0x34 0x0
|
||||
0x1980 0xa6 0x0
|
||||
0x10cc 0xf0 0x0
|
||||
0x18cc 0xf0 0x0
|
||||
0x10d8 0x0f 0x0
|
||||
0x18d8 0x0f 0x0
|
||||
0x10dc 0x00 0x0
|
||||
0x18dc 0x00 0x0
|
||||
0x11a4 0x38 0x0
|
||||
0x19a4 0x38 0x0
|
||||
0x0e3c 0x1d 0x0
|
||||
0x163c 0x1d 0x0
|
||||
0x0e40 0x0c 0x0
|
||||
0x1640 0x0c 0x0
|
||||
0x1190 0x34 0x0
|
||||
0x1990 0x34 0x0
|
||||
0x104c 0x08 0x0
|
||||
0x184c 0x08 0x0
|
||||
0x1050 0x08 0x0
|
||||
0x1850 0x08 0x0
|
||||
0x02dc 0x05 0x0
|
||||
0x0388 0x77 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x03e0 0x0f 0x0
|
||||
0x060c 0x1d 0x0
|
||||
0x0614 0x07 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
pcie1_rp: pcie1_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_msi: qcom,pcie1_msi@17210040 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x17210040 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie2: qcom,pcie@1c10000 {
|
||||
compatible = "qcom,pci-msm";
|
||||
|
||||
reg = <0x01C10000 0x3000>,
|
||||
<0x01C16000 0x2000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40100000 0x100000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
|
||||
|
||||
cell-index = <2>;
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
|
||||
|
||||
interrupt-parent = <&pcie2>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
||||
"int_d";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0xffffffff>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 1 &intc GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &intc GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &intc GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &intc GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-parent = <&pcie2_msi>;
|
||||
|
||||
perst-gpio = <&tlmm 170 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpio = <&tlmm 172 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie2_perst_default
|
||||
&pcie2_clkreq_default
|
||||
&pcie2_wake_default>;
|
||||
pinctrl-1 = <&pcie2_perst_default
|
||||
&pcie2_clkreq_sleep
|
||||
&pcie2_wake_default>;
|
||||
|
||||
gdsc-vdd-supply = <&gcc_pcie_2_gdsc>;
|
||||
vreg-1p8-supply = <&L1E>;
|
||||
vreg-0p9-supply = <&L2E>;
|
||||
vreg-qref-supply = <&L2D>;
|
||||
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||||
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
||||
|
||||
qcom,vreg-1p8-voltage-level = <1200000 1200000 25800>;
|
||||
qcom,vreg-0p9-voltage-level = <880000 880000 186000>;
|
||||
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,vreg-qref-voltage-level = <880000 880000 600>;
|
||||
qcom,bw-scale = /* Gen1 */
|
||||
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen2 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen3 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000
|
||||
/* Gen4 */
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
100000000>;
|
||||
|
||||
interconnect-names = "icc_path";
|
||||
interconnects = <&pcie_noc MASTER_PCIE_4 &mc_virt SLAVE_EBI1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_2_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_PHY_AUX_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>,
|
||||
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
|
||||
<&pcie_2_pipe_clk>,
|
||||
<&pcie_2_phy_aux_clk>;
|
||||
clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src",
|
||||
"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
|
||||
"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
|
||||
"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",
|
||||
"pcie_phy_refgen_clk",
|
||||
"pcie_ddrss_sf_tbu_clk",
|
||||
"pcie_aggre_noc_0_axi_clk",
|
||||
"pcie_phy_aux_clk", "pcie_aggre_noc_pcie_sf_axi_clk",
|
||||
"pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_2_pipe_div2_clk",
|
||||
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk_ext_src";
|
||||
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <0>, <100000000>, <0>,
|
||||
<0>, <0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_2_BCR>,
|
||||
<&gcc GCC_PCIE_2_PHY_BCR>;
|
||||
reset-names = "pcie_2_core_reset",
|
||||
"pcie_2_phy_reset";
|
||||
|
||||
dma-coherent;
|
||||
// qcom,smmu-sid-base = <0x2c00>;
|
||||
// iommu-map = <0x0 &apps_smmu 0x2c00 0x1>,
|
||||
// <0x100 &apps_smmu 0x2c01 0x1>;
|
||||
|
||||
qcom,boot-option = <0x1>;
|
||||
qcom,drv-supported;
|
||||
qcom,drv-l1ss-timeout-us = <5000>;
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,slv-addr-space-size = <0x20000000>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
qcom,l1-2-th-scale = <2>;
|
||||
qcom,l1-2-th-value = <150>;
|
||||
|
||||
qcom,pcie-phy-ver = <109>;
|
||||
qcom,phy-status-offset = <0x1214>;
|
||||
qcom,phy-status-bit = <7>;
|
||||
qcom,phy-power-down-offset = <0x1240>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x00c0 0x01 0x0
|
||||
0x00cc 0x31 0x0
|
||||
0x00d0 0x01 0x0
|
||||
0x0060 0xde 0x0
|
||||
0x0064 0x07 0x0
|
||||
0x0000 0x4c 0x0
|
||||
0x0004 0x06 0x0
|
||||
0x00e0 0x90 0x0
|
||||
0x00e4 0x82 0x0
|
||||
0x00f4 0x0f 0x0
|
||||
0x0070 0x06 0x0
|
||||
0x0010 0x06 0x0
|
||||
0x0074 0x16 0x0
|
||||
0x0014 0x16 0x0
|
||||
0x0078 0x36 0x0
|
||||
0x0018 0x36 0x0
|
||||
0x0110 0x08 0x0
|
||||
0x00bc 0x0e 0x0
|
||||
0x0120 0x42 0x0
|
||||
0x0080 0x0a 0x0
|
||||
0x0084 0x1a 0x0
|
||||
0x0020 0x14 0x0
|
||||
0x0024 0x34 0x0
|
||||
0x0088 0x82 0x0
|
||||
0x0028 0x68 0x0
|
||||
0x0090 0x55 0x0
|
||||
0x0094 0x55 0x0
|
||||
0x0098 0x03 0x0
|
||||
0x0030 0xab 0x0
|
||||
0x0034 0xaa 0x0
|
||||
0x0038 0x02 0x0
|
||||
0x0140 0x14 0x0
|
||||
0x0164 0x34 0x0
|
||||
0x003c 0x01 0x0
|
||||
0x001c 0x04 0x0
|
||||
0x0174 0x16 0x0
|
||||
0x01bc 0x0f 0x0
|
||||
0x0170 0xa0 0x0
|
||||
0x11a4 0x38 0x0
|
||||
0x10dc 0x00 0x0
|
||||
0x1160 0xbf 0x0
|
||||
0x1164 0xbf 0x0
|
||||
0x1168 0xb7 0x0
|
||||
0x116c 0xea 0x0
|
||||
0x115c 0x3f 0x0
|
||||
0x1174 0xdc 0x0
|
||||
0x1178 0x5c 0x0
|
||||
0x117c 0x34 0x0
|
||||
0x1180 0xa6 0x0
|
||||
0x1170 0xdc 0x0
|
||||
0x1190 0x34 0x0
|
||||
0x10cc 0xf0 0x0
|
||||
0x104c 0x08 0x0
|
||||
0x1050 0x08 0x0
|
||||
0x10d8 0x0f 0x0
|
||||
0x1118 0x1c 0x0
|
||||
0x10f8 0x07 0x0
|
||||
0x11f8 0x08 0x0
|
||||
0x0e84 0x15 0x0
|
||||
0x0e90 0x3f 0x0
|
||||
0x0ee4 0x02 0x0
|
||||
0x0e40 0x06 0x0
|
||||
0x0e3c 0x17 0x0
|
||||
0x19a4 0x38 0x0
|
||||
0x18dc 0x00 0x0
|
||||
0x1960 0xbf 0x0
|
||||
0x1964 0xbf 0x0
|
||||
0x1968 0xb7 0x0
|
||||
0x196c 0xea 0x0
|
||||
0x195c 0x3f 0x0
|
||||
0x1974 0xdc 0x0
|
||||
0x1978 0x5c 0x0
|
||||
0x197c 0x34 0x0
|
||||
0x1980 0xa6 0x0
|
||||
0x1970 0xdc 0x0
|
||||
0x1990 0x34 0x0
|
||||
0x18cc 0xf0 0x0
|
||||
0x184c 0x08 0x0
|
||||
0x1850 0x08 0x0
|
||||
0x18d8 0x0f 0x0
|
||||
0x1918 0x1c 0x0
|
||||
0x18f8 0x07 0x0
|
||||
0x19f8 0x08 0x0
|
||||
0x1684 0x15 0x0
|
||||
0x1690 0x3f 0x0
|
||||
0x16e4 0x02 0x0
|
||||
0x1640 0x06 0x0
|
||||
0x163c 0x17 0x0
|
||||
0x02dc 0x05 0x0
|
||||
0x0388 0x77 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x03e0 0x0f 0x0
|
||||
0x060c 0x1d 0x0
|
||||
0x0614 0x07 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x03d0 0x8c 0x0
|
||||
0x1424 0x00 0x0
|
||||
0x1428 0x00 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
pcie2_rp: pcie2_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_msi: qcom,pcie2_msi@17210040 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x17210040 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
};
|
||||
@@ -26,4 +26,166 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie0 {
|
||||
pcie0_perst_default: pcie0_perst_default {
|
||||
mux {
|
||||
pins = "gpio117";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio117";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_default: pcie0_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio118";
|
||||
function = "pcie0_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio118";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_default: pcie0_wake_default {
|
||||
mux {
|
||||
pins = "gpio119";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio119";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio118";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio118";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie1 {
|
||||
pcie1_perst_default: pcie1_perst_default {
|
||||
mux {
|
||||
pins = "gpio141";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio141";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_default: pcie1_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio142";
|
||||
function = "pcie1_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio142";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_wake_default: pcie1_wake_default {
|
||||
mux {
|
||||
pins = "gpio143";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio143";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio142";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio142";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie2 {
|
||||
pcie2_perst_default: pcie2_perst_default {
|
||||
mux {
|
||||
pins = "gpio170";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio170";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_default: pcie2_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio171";
|
||||
function = "pcie1_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio171";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_wake_default: pcie2_wake_default {
|
||||
mux {
|
||||
pins = "gpio172";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio172";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio171";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio171";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -42,6 +42,63 @@
|
||||
clocks = <&xo_board>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
pcie0: qcom,pcie@1c00000 {
|
||||
status = "disabled";
|
||||
reg = <0x01c00000 0x3000>,
|
||||
<0x01c06000 0x2000>,
|
||||
<0x60000000 0xf1d>,
|
||||
<0x60000f20 0xa8>,
|
||||
<0x60001000 0x1000>,
|
||||
<0x60100000 0x100000>,
|
||||
<0x1c04000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
|
||||
"rumi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l0s-supported;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
|
||||
pcie1: qcom,pcie@1c08000 {
|
||||
status = "disabled";
|
||||
reg = <0x01c08000 0x3000>,
|
||||
<0x01c0e000 0x2000>,
|
||||
<0x64000000 0xf1d>,
|
||||
<0x64000f20 0xa8>,
|
||||
<0x64001000 0x1000>,
|
||||
<0x64100000 0x100000>,
|
||||
<0x1c0d000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
|
||||
"rumi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l0s-supported;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
|
||||
pcie2: qcom,pcie@1c10000 {
|
||||
status = "ok";
|
||||
reg = <0x01c10000 0x3000>,
|
||||
<0x01c16000 0x2000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40100000 0x100000>,
|
||||
<0x01c14000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
|
||||
"rumi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l0s-supported;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
|
||||
@@ -1064,3 +1064,4 @@
|
||||
#include "anorak-stub-regulator.dtsi"
|
||||
#include "anorak-dma-heaps.dtsi"
|
||||
#include "ipcc-test.dtsi"
|
||||
#include "anorak-pcie.dtsi"
|
||||
|
||||
Reference in New Issue
Block a user