mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: qcom: Add support for CAPE clock controllers
Update the clock controller nodes for CAPE and also split the clocks/GDSC shared between waipio and cape target. Change-Id: I5cbe8107f1513d52e7ad70f5895694141afed23b
This commit is contained in:
Taniya Das
@@ -1,3 +1,4 @@
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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@@ -263,6 +264,8 @@
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};
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};
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#include "waipio-clock.dtsi"
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -370,6 +373,11 @@
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<CONTROL_TCS 0>, /* PDC wakeup values will be written from TZ */
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<FAST_PATH_TCS 1>;
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power-domains = <&CLUSTER_PD>;
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clock_rpmh: qcom,rpmhclk {
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compatible = "qcom,waipio-rpmh-clk";
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#clock-cells = <1>;
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};
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};
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cpuss-sleep-stats@17800054 {
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@@ -501,7 +509,26 @@
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reg-names = "rmtfs";
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qcom,client-id = <0x00000001>;
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};
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};
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&clock_gcc {
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compatible = "qcom,cape-gcc", "syscon";
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};
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&clock_videocc {
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compatible = "qcom,cape-videocc", "syscon";
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};
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&clock_camcc {
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compatible = "qcom,cape-camcc", "syscon";
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};
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&clock_dispcc {
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compatible = "qcom,cape-dispcc", "syscon";
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};
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&clock_gpucc {
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compatible = "qcom,cape-gpucc", "syscon";
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};
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#include "cape-pinctrl.dtsi"
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441
qcom/waipio-clock.dtsi
Normal file
441
qcom/waipio-clock.dtsi
Normal file
@@ -0,0 +1,441 @@
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#include <dt-bindings/clock/qcom,camcc-waipio.h>
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#include <dt-bindings/clock/qcom,dispcc-waipio.h>
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#include <dt-bindings/clock/qcom,gcc-waipio.h>
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#include <dt-bindings/clock/qcom,gpucc-waipio.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,videocc-waipio.h>
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&soc {
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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};
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clock_gcc: clock-controller@100000 {
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compatible = "qcom,waipio-gcc", "syscon";
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reg = <0x100000 0x1f4200>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mxa-supply = <&VDD_MXA_LEVEL>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&sleep_clk>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_videocc: clock-controller@aaf0000 {
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compatible = "qcom,waipio-videocc", "syscon";
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reg = <0xaaf0000 0x10000>;
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reg-name = "cc_base";
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vdd_mm-supply = <&VDD_MM_LEVEL>;
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vdd_mxc-supply = <&VDD_MXC_LEVEL>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&clock_gcc GCC_VIDEO_AHB_CLK>;
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clock-names = "bi_tcxo",
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"sleep_clk",
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"iface";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_camcc: clock-controller@ade0000 {
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compatible = "qcom,waipio-camcc", "syscon";
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reg = <0xade0000 0x20000>;
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reg-names = "cc_base";
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vdd_mm-supply = <&VDD_MM_LEVEL>;
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vdd_mxa-supply = <&VDD_MXA_LEVEL>;
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vdd_mxc-supply = <&VDD_MXC_LEVEL>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&clock_gcc GCC_CAMERA_AHB_CLK>;
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clock-names = "bi_tcxo",
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"sleep_clk",
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"iface";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_dispcc: clock-controller@af00000 {
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compatible = "qcom,waipio-dispcc", "syscon";
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reg = <0xaf00000 0x20000>;
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reg-name = "cc_base";
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vdd_mm-supply = <&VDD_MM_LEVEL>;
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vdd_mxa-supply = <&VDD_MXA_LEVEL>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&clock_gcc GCC_VIDEO_AHB_CLK>;
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clock-names = "bi_tcxo",
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"sleep_clk",
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"iface";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_gpucc: clock-controller@3d90000 {
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compatible = "qcom,waipio-gpucc", "syscon";
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clock-output-names = "gpucc_clocks";
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reg = <0x3d90000 0xa000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_mx-supply = <&VDD_MXA_LEVEL>;
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vdd_mxc-supply = <&VDD_MXC_LEVEL>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&clock_gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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clock-names = "bi_tcxo",
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"gpll0_out_main",
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"gpll0_out_main_div";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock_apsscc: syscon@17a80000 {
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compatible = "syscon";
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reg = <0x17a80000 0x21000>;
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};
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clock_mccc: syscon@190ba000 {
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compatible = "syscon";
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reg = <0x190ba000 0x54>;
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};
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clock_debugcc: clock-controller@0 {
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compatible = "qcom,waipio-debugcc";
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qcom,gcc = <&clock_gcc>;
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qcom,videocc = <&clock_videocc>;
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qcom,dispcc = <&clock_dispcc>;
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qcom,camcc = <&clock_camcc>;
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qcom,gpucc = <&clock_gpucc>;
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qcom,apsscc = <&clock_apsscc>;
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qcom,mccc = <&clock_mccc>;
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clock-names = "xo_clk_src";
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clocks = <&clock_rpmh RPMH_CXO_CLK>;
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#clock-cells = <1>;
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};
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cpufreq_hw: qcom,cpufreq-hw {
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compatible = "qcom,cpufreq-hw-epss";
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reg = <0x17d91000 0x1000>,
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<0x17d92000 0x1000>,
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<0x17d93000 0x1000>,
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<0x17d09804 0x4>,
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<0x17d09808 0x4>,
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<0x17d0980c 0x4>;
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reg-names = "freq-domain0",
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"freq-domain1",
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"freq-domain2",
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"pdmem-domain0",
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"pdmem-domain1",
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"pdmem-domain2";
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clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_GPLL0>;
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clock-names = "xo", "alternate";
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qcom,lut-row-size = <4>;
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qcom,skip-enable-check;
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qcom,perf-lock-support;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dcvsh0_int",
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"dcvsh1_int",
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"dcvsh2_int";
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#freq-domain-cells = <2>;
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};
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qcom,cpufreq-hw-debug {
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compatible = "qcom,cpufreq-hw-epss-debug";
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qcom,freq-hw-domain = <&cpufreq_hw 0>,
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<&cpufreq_hw 1>,
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<&cpufreq_hw 2>;
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};
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/* CAM_CC GDSCs */
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cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
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compatible = "qcom,gdsc";
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reg = <0xadf0004 0x4>;
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regulator-name = "cam_cc_bps_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
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compatible = "qcom,gdsc";
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reg = <0xadf1004 0x4>;
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regulator-name = "cam_cc_ife_0_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
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compatible = "qcom,gdsc";
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reg = <0xadf2004 0x4>;
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regulator-name = "cam_cc_ife_1_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ife_2_gdsc: qcom,gdsc@adf2050 {
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compatible = "qcom,gdsc";
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reg = <0xadf2050 0x4>;
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regulator-name = "cam_cc_ife_2_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_ipe_0_gdsc: qcom,gdsc@adf0078 {
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compatible = "qcom,gdsc";
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reg = <0xadf0078 0x4>;
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regulator-name = "cam_cc_ipe_0_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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cam_cc_sbi_gdsc: qcom,gdsc@adf00d0 {
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compatible = "qcom,gdsc";
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reg = <0xadf00d0 0x4>;
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regulator-name = "cam_cc_sbi_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_sfe_0_gdsc: qcom,gdsc@adf3050 {
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compatible = "qcom,gdsc";
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reg = <0xadf3050 0x4>;
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regulator-name = "cam_cc_sfe_0_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_sfe_1_gdsc: qcom,gdsc@adf3098 {
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compatible = "qcom,gdsc";
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reg = <0xadf3098 0x4>;
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regulator-name = "cam_cc_sfe_1_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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cam_cc_titan_top_gdsc: qcom,gdsc@adf31dc {
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compatible = "qcom,gdsc";
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reg = <0xadf31dc 0x4>;
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regulator-name = "cam_cc_titan_top_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
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parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
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qcom,retain-regs;
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};
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/* DISP_CC GDSCs */
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disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
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compatible = "qcom,gdsc";
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reg = <0xaf09000 0x4>;
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regulator-name = "disp_cc_mdss_core_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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proxy-supply = <&disp_cc_mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
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compatible = "qcom,gdsc";
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reg = <0xaf0b000 0x4>;
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regulator-name = "disp_cc_mdss_core_int2_gdsc";
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qcom,gds-timeout = <500>;
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clock-names = "ahb_clk";
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clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
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parent-supply = <&VDD_MM_LEVEL>;
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qcom,support-hw-trigger;
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qcom,retain-regs;
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};
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gcc_apcs_gdsc_vote_ctrl: syscon@162128 {
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compatible = "syscon";
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reg = <0x162128 0x4>;
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};
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/* GCC GDSCs */
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gcc_pcie_0_gdsc: qcom,gdsc@17b004 {
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compatible = "qcom,gdsc";
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reg = <0x17b004 0x4>;
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regulator-name = "gcc_pcie_0_gdsc";
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qcom,gds-timeout = <500>;
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,no-status-check-on-disable;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
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};
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gcc_pcie_1_gdsc: qcom,gdsc@19d004 {
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compatible = "qcom,gdsc";
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reg = <0x19d004 0x4>;
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regulator-name = "gcc_pcie_1_gdsc";
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qcom,gds-timeout = <500>;
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,retain-regs;
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qcom,no-status-check-on-disable;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
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};
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gcc_ufs_phy_gdsc: qcom,gdsc@187004 {
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compatible = "qcom,gdsc";
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reg = <0x187004 0x4>;
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regulator-name = "gcc_ufs_phy_gdsc";
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qcom,gds-timeout = <500>;
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parent-supply = <&VDD_CX_LEVEL>;
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proxy-supply = <&gcc_ufs_phy_gdsc>;
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qcom,proxy-consumer-enable;
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qcom,retain-regs;
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@149004 {
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compatible = "qcom,gdsc";
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reg = <0x149004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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qcom,gds-timeout = <500>;
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proxy-supply = <&gcc_usb30_prim_gdsc>;
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qcom,proxy-consumer-enable;
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qcom,retain-regs;
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};
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/* GPU_CC GDSCs */
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gpu_cc_cx_hw_ctrl: syscon@3d9953c {
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compatible = "syscon";
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reg = <0x3d9953c 0x4>;
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};
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gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
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compatible = "qcom,gdsc";
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reg = <0x3d99108 0x4>;
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regulator-name = "gpu_cc_cx_gdsc";
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hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
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parent-supply = <&VDD_CX_LEVEL>;
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qcom,no-status-check-on-disable;
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qcom,clk-dis-wait-val = <8>;
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qcom,gds-timeout = <500>;
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qcom,retain-regs;
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};
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gpu_cc_gx_domain_addr: syscon@3d99504 {
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compatible = "syscon";
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reg = <0x3d99504 0x4>;
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};
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||||
|
||||
gpu_cc_gx_sw_reset: syscon@3d99058 {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d99058 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_acd_reset: syscon@3d99358 {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d99358 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d9958c 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x3d9905c 0x4>;
|
||||
regulator-name = "gpu_cc_gx_gdsc";
|
||||
domain-addr = <&gpu_cc_gx_domain_addr>;
|
||||
sw-reset = <&gpu_cc_gx_sw_reset>,
|
||||
<&gpu_cc_gx_acd_reset>,
|
||||
<&gpu_cc_gx_acd_iroot_reset>;
|
||||
parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
|
||||
qcom,reset-aon-logic;
|
||||
qcom,retain-regs;
|
||||
qcom,gds-timeout = <500>;
|
||||
};
|
||||
|
||||
/* VIDEO_CC GDSCs */
|
||||
video_cc_mvs0_gdsc: qcom,gdsc@aaf809c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf809C 0x4>;
|
||||
regulator-name = "video_cc_mvs0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&video_cc_mvs0c_gdsc>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs0c_gdsc: qcom,gdsc@aaf804c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf804c 0x4>;
|
||||
regulator-name = "video_cc_mvs0c_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs1_gdsc: qcom,gdsc@aaf80c0 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf80c0 0x4>;
|
||||
regulator-name = "video_cc_mvs1_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&video_cc_mvs1c_gdsc>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs1c_gdsc: qcom,gdsc@aaf8074 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf8074 0x4>;
|
||||
regulator-name = "video_cc_mvs1c_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
};
|
||||
441
qcom/waipio.dtsi
441
qcom/waipio.dtsi
@@ -1,10 +1,4 @@
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,camcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-waipio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
@@ -667,6 +661,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
#include "waipio-clock.dtsi"
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -1568,22 +1564,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
xo_board: xo_board {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <76800000>;
|
||||
clock-output-names = "xo_board";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
clock-output-names = "sleep_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ipcc_mproc: qcom,ipcc@ed18000 {
|
||||
compatible = "qcom,ipcc";
|
||||
reg = <0xed18000 0x1000>;
|
||||
@@ -1717,423 +1697,6 @@
|
||||
msgq-label = <3>;
|
||||
};
|
||||
|
||||
/* CAM_CC GDSCs */
|
||||
cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf0004 0x4>;
|
||||
regulator-name = "cam_cc_bps_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf1004 0x4>;
|
||||
regulator-name = "cam_cc_ife_0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf2004 0x4>;
|
||||
regulator-name = "cam_cc_ife_1_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_ife_2_gdsc: qcom,gdsc@adf2050 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf2050 0x4>;
|
||||
regulator-name = "cam_cc_ife_2_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_ipe_0_gdsc: qcom,gdsc@adf0078 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf0078 0x4>;
|
||||
regulator-name = "cam_cc_ipe_0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_sbi_gdsc: qcom,gdsc@adf00d0 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf00d0 0x4>;
|
||||
regulator-name = "cam_cc_sbi_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_sfe_0_gdsc: qcom,gdsc@adf3050 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf3050 0x4>;
|
||||
regulator-name = "cam_cc_sfe_0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_sfe_1_gdsc: qcom,gdsc@adf3098 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf3098 0x4>;
|
||||
regulator-name = "cam_cc_sfe_1_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
cam_cc_titan_top_gdsc: qcom,gdsc@adf31dc {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xadf31dc 0x4>;
|
||||
regulator-name = "cam_cc_titan_top_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
/* DISP_CC GDSCs */
|
||||
disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaf09000 0x4>;
|
||||
regulator-name = "disp_cc_mdss_core_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
proxy-supply = <&disp_cc_mdss_core_gdsc>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaf0b000 0x4>;
|
||||
regulator-name = "disp_cc_mdss_core_int2_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
gcc_apcs_gdsc_vote_ctrl: syscon@162128 {
|
||||
compatible = "syscon";
|
||||
reg = <0x162128 0x4>;
|
||||
};
|
||||
|
||||
/* GCC GDSCs */
|
||||
gcc_pcie_0_gdsc: qcom,gdsc@17b004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x17b004 0x4>;
|
||||
regulator-name = "gcc_pcie_0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
qcom,no-status-check-on-disable;
|
||||
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
|
||||
};
|
||||
|
||||
gcc_pcie_1_gdsc: qcom,gdsc@19d004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x19d004 0x4>;
|
||||
regulator-name = "gcc_pcie_1_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
qcom,no-status-check-on-disable;
|
||||
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
|
||||
};
|
||||
|
||||
gcc_ufs_phy_gdsc: qcom,gdsc@187004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x187004 0x4>;
|
||||
regulator-name = "gcc_ufs_phy_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
proxy-supply = <&gcc_ufs_phy_gdsc>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
gcc_usb30_prim_gdsc: qcom,gdsc@149004 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x149004 0x4>;
|
||||
regulator-name = "gcc_usb30_prim_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
proxy-supply = <&gcc_usb30_prim_gdsc>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
/* GPU_CC GDSCs */
|
||||
gpu_cc_cx_hw_ctrl: syscon@3d9953c {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d9953c 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x3d99108 0x4>;
|
||||
regulator-name = "gpu_cc_cx_gdsc";
|
||||
hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
qcom,no-status-check-on-disable;
|
||||
qcom,clk-dis-wait-val = <8>;
|
||||
qcom,gds-timeout = <500>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
gpu_cc_gx_domain_addr: syscon@3d99504 {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d99504 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_sw_reset: syscon@3d99058 {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d99058 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_acd_reset: syscon@3d99358 {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d99358 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
|
||||
compatible = "syscon";
|
||||
reg = <0x3d9958c 0x4>;
|
||||
};
|
||||
|
||||
gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0x3d9905c 0x4>;
|
||||
regulator-name = "gpu_cc_gx_gdsc";
|
||||
domain-addr = <&gpu_cc_gx_domain_addr>;
|
||||
sw-reset = <&gpu_cc_gx_sw_reset>,
|
||||
<&gpu_cc_gx_acd_reset>,
|
||||
<&gpu_cc_gx_acd_iroot_reset>;
|
||||
parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
|
||||
qcom,reset-aon-logic;
|
||||
qcom,retain-regs;
|
||||
qcom,gds-timeout = <500>;
|
||||
};
|
||||
|
||||
/* VIDEO_CC GDSCs */
|
||||
video_cc_mvs0_gdsc: qcom,gdsc@aaf809c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf809C 0x4>;
|
||||
regulator-name = "video_cc_mvs0_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&video_cc_mvs0c_gdsc>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs0c_gdsc: qcom,gdsc@aaf804c {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf804c 0x4>;
|
||||
regulator-name = "video_cc_mvs0c_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs1_gdsc: qcom,gdsc@aaf80c0 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf80c0 0x4>;
|
||||
regulator-name = "video_cc_mvs1_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&video_cc_mvs1c_gdsc>;
|
||||
qcom,support-hw-trigger;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
video_cc_mvs1c_gdsc: qcom,gdsc@aaf8074 {
|
||||
compatible = "qcom,gdsc";
|
||||
reg = <0xaaf8074 0x4>;
|
||||
regulator-name = "video_cc_mvs1c_gdsc";
|
||||
qcom,gds-timeout = <500>;
|
||||
clock-names = "ahb_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
clock_gcc: qcom,gcc@100000 {
|
||||
compatible = "qcom,waipio-gcc", "syscon";
|
||||
reg = <0x100000 0x1f4200>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clock_videocc: qcom,videocc@aaf0000 {
|
||||
compatible = "qcom,waipio-videocc", "syscon";
|
||||
reg = <0xaaf0000 0x10000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clock_camcc: qcom,camcc@ade0000 {
|
||||
compatible = "qcom,waipio-camcc", "syscon";
|
||||
reg = <0xade0000 0x20000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&clock_gcc GCC_CAMERA_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clock_dispcc: qcom,dispcc@af00000 {
|
||||
compatible = "qcom,waipio-dispcc", "syscon";
|
||||
reg = <0xaf00000 0x20000>;
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&clock_gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clock_gpucc: qcom,gpucc@3d90000 {
|
||||
compatible = "qcom,waipio-gpucc", "syscon";
|
||||
clock-output-names = "gpucc_clocks";
|
||||
reg = <0x3d90000 0xA000>;
|
||||
reg-names = "cc_base";
|
||||
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
||||
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&clock_gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&clock_gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gpll0_out_main",
|
||||
"gpll0_out_main_div";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clock_apsscc: syscon@17A80000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x17A80000 0x21000>;
|
||||
};
|
||||
|
||||
clock_mccc: syscon@190ba000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x190ba000 0x54>;
|
||||
};
|
||||
|
||||
clock_debugcc: qcom,cc-debug {
|
||||
compatible = "qcom,waipio-debugcc";
|
||||
qcom,gcc = <&clock_gcc>;
|
||||
qcom,videocc = <&clock_videocc>;
|
||||
qcom,dispcc = <&clock_dispcc>;
|
||||
qcom,camcc = <&clock_camcc>;
|
||||
qcom,gpucc = <&clock_gpucc>;
|
||||
qcom,apsscc = <&clock_apsscc>;
|
||||
qcom,mccc = <&clock_mccc>;
|
||||
clock-names = "xo_clk_src";
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cpufreq_hw: qcom,cpufreq-hw {
|
||||
compatible = "qcom,cpufreq-hw-epss";
|
||||
reg = <0x17D91000 0x1000>,
|
||||
<0x17D92000 0x1000>,
|
||||
<0x17D93000 0x1000>,
|
||||
<0x17D09804 0x4>,
|
||||
<0x17D09808 0x4>,
|
||||
<0x17D0980C 0x4>;
|
||||
reg-names = "freq-domain0",
|
||||
"freq-domain1",
|
||||
"freq-domain2",
|
||||
"pdmem-domain0",
|
||||
"pdmem-domain1",
|
||||
"pdmem-domain2";
|
||||
clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
qcom,lut-row-size = <4>;
|
||||
qcom,skip-enable-check;
|
||||
qcom,perf-lock-support;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dcvsh0_int",
|
||||
"dcvsh1_int",
|
||||
"dcvsh2_int";
|
||||
#freq-domain-cells = <2>;
|
||||
};
|
||||
|
||||
qcom,cpufreq-hw-debug {
|
||||
compatible = "qcom,cpufreq-hw-epss-debug";
|
||||
qcom,freq-hw-domain = <&cpufreq_hw 0>,
|
||||
<&cpufreq_hw 1>,
|
||||
<&cpufreq_hw 2>;
|
||||
};
|
||||
|
||||
clk_virt: interconnect@0 {
|
||||
compatible = "qcom,waipio-clk_virt";
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
Reference in New Issue
Block a user