Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: camera: remove cphy clock entry from tfe csid

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tfe csid node does not need to have cphy clock values.
csid node need to set only default clock. Required  clock value
will be set by the phy driver.

CRs-Fixed: 2796075
Change-Id: Ide1b2b2e0e124357ed20589e0f2bb0431b579009
This commit is contained in:
Ravikishore Pampana
2020-10-06 16:51:52 +05:30
committed by Gerrit - the friendly Code Review server
parent 74908cc52a
commit a7503b7ef9
3 changed files with 21 additions and 21 deletions
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18
bengal-camera.dtsi
View File

@@ -616,9 +616,9 @@
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CLK>;
clock-rates =
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
<240000000 0 0 0 256000000 0>,
<384000000 0 0 0 460800000 0>,
<426400000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
@@ -681,9 +681,9 @@
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CLK>;
clock-rates =
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
<240000000 0 0 0 256000000 0>,
<384000000 0 0 0 460800000 0>,
<426400000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
@@ -746,9 +746,9 @@
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CLK>;
clock-rates =
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
<240000000 0 0 0 256000000 0>,
<384000000 0 0 0 460800000 0>,
<426400000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";

18
holi-camera.dtsi
View File

@@ -731,9 +731,9 @@
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CLK>;
clock-rates =
<300000000 0 240000000 0 300000000 0>,
<426400000 0 341333333 0 460800000 0>,
<466500000 0 384000000 0 576000000 0>;
<300000000 0 0 0 300000000 0>,
<426400000 0 0 0 460800000 0>,
<466500000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
@@ -795,9 +795,9 @@
<&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_1_CLK>;
clock-rates =
<300000000 0 240000000 0 300000000 0>,
<426400000 0 341333333 0 460800000 0>,
<466500000 0 384000000 0 576000000 0>;
<300000000 0 0 0 300000000 0>,
<426400000 0 0 0 460800000 0>,
<466500000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";
@@ -859,9 +859,9 @@
<&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_2_CLK>;
clock-rates =
<300000000 0 240000000 0 300000000 0>,
<426400000 0 341333333 0 460800000 0>,
<466500000 0 384000000 0 576000000 0>;
<300000000 0 0 0 300000000 0>,
<426400000 0 0 0 460800000 0>,
<466500000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";

6
scuba-camera.dtsi
View File

@@ -564,9 +564,9 @@
<&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
<&gcc GCC_CAMSS_TFE_0_CLK>;
clock-rates =
<240000000 0 240000000 0 256000000 0>,
<384000000 0 341333333 0 460800000 0>,
<426400000 0 384000000 0 576000000 0>;
<240000000 0 0 0 256000000 0>,
<384000000 0 0 0 460800000 0>,
<426400000 0 0 0 576000000 0>;
clock-cntl-level = "svs", "svs_l1", "turbo";
src-clock-name = "tfe_csid_clk_src";
clock-control-debugfs = "true";