Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: update PCIe LTR value to 150us for Waipio

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On Waipio, PCIe L1.2 exit is about 150us. Therefore update PCIe
so that it will program all PCI devices LTR register with 150us.
Devices can use this value to deterine if L1.2 should be entered
or not based on their latency requirement.

Change-Id: If0c4af02654a5277b9d7f702af2fe16aaef45b8a
This commit is contained in:
Hemant Kumar
2021-05-18 16:56:31 -07:00
parent 009714a60a
commit adfba7b03e
1 changed files with 3 additions and 1 deletions
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4
qcom/waipio-pcie.dtsi
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@@ -115,7 +115,7 @@
qcom,drv-supported;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <70>;
qcom,l1-2-th-value = <150>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
@@ -363,6 +363,8 @@
qcom,slv-addr-space-size = <0x20000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,pcie-phy-ver = <103>;
qcom,phy-status-offset = <0x1214>;