Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: add ufs device support for Lahaina

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Add support for embedded UFS device support.
Add support for RUMI pre-sil validation.

Change-Id: I1a9117120800fd7066fff0a9382a560150151910
This commit is contained in:
Asutosh Das
2019-06-25 11:38:47 +05:30
parent c98fe1bdcf
commit aea869e3c4
3 changed files with 95 additions and 2 deletions
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4
bindings/ufs/ufs-qcom.txt
View File

@@ -11,7 +11,9 @@ Required properties:
"qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
"qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
"qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
present on MSM8996 chipset.
present on MSM8996 chipset,
"qcom,ufs-phy-qrbtc-sdm845" for phy support
for sdm845 emulation.
- reg : should contain PHY register address space (mandatory),
- reg-names : indicates various resources passed to driver (via reg proptery) by name.
Required "reg-names" is "phy_mem".

32
qcom/lahaina-rumi.dtsi
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@@ -0,0 +1,32 @@
#include "lahaina.dtsi"
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&pm8350_l5>;
vdda-pll-supply = <&pm8350_l6>;
vdda-phy-max-microamp = <85700>;
vdda-pll-max-microamp = <18300>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
vcc-supply = <&pm8350_l7>;
vcc-max-microamp = <800000>;
vccq-supply = <&pm8350_l9>;
vccq-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&pm8350_l9>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
status = "ok";
};

61
qcom/lahaina.dtsi
View File

@@ -20,7 +20,9 @@
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases { };
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
};
cpus {
#address-cells = <2>;
@@ -532,6 +534,63 @@
compatible = "qcom,lahaina-system_noc";
#interconnect-cells = <1>;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d8700 0xe10>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_aux_clk";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "disabled";
};
};
#include "lahaina-pinctrl.dtsi"