ARM: dts: msm: jpeg misr enable

Enable jpeg misr for both DMA and Encoder and also
supports base address for camnoc.

CRs-Fixed: 3012752
Change-Id: I3e8ef8907214adcf779d5a28a420c50b1a76ddb1
Signed-off-by: Dharmender Sharma <dharshar@qti.qualcomm.com>
This commit is contained in:
Dharmender Sharma
2021-07-29 00:03:52 +05:30
committed by Gerrit - the friendly Code Review server
parent 10d8ee5912
commit b07ebf86e8
4 changed files with 38 additions and 24 deletions

View File

@@ -48,6 +48,7 @@ Required Node Structure
=======================
Encoder/DMA Nodes provide interface for JPEG driver about
the device register map, interrupt map, clocks and regulators.
Compatible string definition should be based on target.
- cell-index
Usage: required
@@ -58,6 +59,13 @@ the device register map, interrupt map, clocks and regulators.
Usage: required
Value type: <string>
Definition: Should be "qcom,cam_jpeg_enc".
Definition: Should be "qcom,cam_jpeg_enc_165".
Definition: Should be "qcom,cam_jpeg_enc_580".
Definition: Should be "qcom,cam_jpeg_enc_680".
Definition: Should be "qcom,cam_jpeg_dma".
Definition: Should be "qcom,cam_jpeg_dma_165".
Definition: Should be "qcom,cam_jpeg_dma_580".
Definition: Should be "qcom,cam_jpeg_dma_680".
- reg-names
Usage: optional

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@@ -1875,10 +1875,11 @@
cam_jpeg_enc: qcom,jpegenc {
cell-index = <0>;
compatible = "qcom,cam_jpeg_enc";
reg-names = "jpege_hw";
reg = <0xac53000 0x4000>;
reg-cam-base = <0x53000>;
compatible = "qcom,cam_jpeg_enc_580";
reg-names = "jpege_hw","cam_camnoc";
reg = <0xac53000 0x4000>,
<0x0ac42000 0x8000>;
reg-cam-base = <0x53000 0x42000>;
interrupt-names = "jpeg";
interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";
@@ -1901,10 +1902,11 @@
cam_jpeg_dma: qcom,jpegdma {
cell-index = <0>;
compatible = "qcom,cam_jpeg_dma";
reg-names = "jpegdma_hw";
reg = <0xac57000 0x4000>;
reg-cam-base = <0x57000>;
compatible = "qcom,cam_jpeg_dma_580";
reg-names = "jpegdma_hw", "cam_camnoc";
reg = <0xac57000 0x4000>,
<0x0ac42000 0x8000>;
reg-cam-base = <0x57000 0x42000>;
interrupt-names = "jpegdma";
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";

View File

@@ -2636,10 +2636,11 @@
cam_jpeg_enc: qcom,jpegenc@ac2a000 {
cell-index = <0>;
compatible = "qcom,cam_jpeg_enc";
reg-names = "jpege_hw";
reg = <0xac2a000 0x1000>;
reg-cam-base = <0x2a000>;
compatible = "qcom,cam_jpeg_enc_680";
reg-names = "jpege_hw", "cam_camnoc";
reg = <0xac2a000 0x1000>,
<0x0ac19000 0x9000>;
reg-cam-base = <0x2a000 0x19000>;
interrupt-names = "jpeg";
interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
@@ -2663,10 +2664,11 @@
cam_jpeg_dma: qcom,jpegdma@ac2b000 {
cell-index = <0>;
compatible = "qcom,cam_jpeg_dma";
reg-names = "jpegdma_hw";
reg = <0xac2b000 0x1000>;
reg-cam-base = <0x2b000>;
compatible = "qcom,cam_jpeg_dma_680";
reg-names = "jpegdma_hw", "cam_camnoc";
reg = <0xac2b000 0x1000>,
<0x0ac19000 0x9000>;
reg-cam-base = <0x2b000 0x19000>;
interrupt-names = "jpegdma";
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";

View File

@@ -1052,10 +1052,11 @@
cam_jpeg_enc: qcom,jpegenc {
cell-index = <0>;
compatible = "qcom,cam_jpeg_enc";
reg-names = "jpege_hw";
reg = <0xac4e000 0x4000>;
reg-cam-base = <0x4e000>;
compatible = "qcom,cam_jpeg_enc_165";
reg-names = "jpege_hw", "cam_camnoc";
reg = <0xac4e000 0x4000>,
<0x0ac9f000 0x10000>;
reg-cam-base = <0x4e000 0x9f000>;
interrupt-names = "jpeg";
interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";
@@ -1078,10 +1079,11 @@
cam_jpeg_dma: qcom,jpegdma {
cell-index = <0>;
compatible = "qcom,cam_jpeg_dma";
reg-names = "jpegdma_hw";
reg = <0xac52000 0x4000>;
reg-cam-base = <0x52000>;
compatible = "qcom,cam_jpeg_dma_165";
reg-names = "jpegdma_hw", "cam_camnoc";
reg = <0xac52000 0x4000>,
<0x0ac9f000 0x10000>;
reg-cam-base = <0x52000 0x9f000>;
interrupt-names = "jpegdma";
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";