Merge "ARM: dts: msm: remove display carveout heap for ravelin 4gb variant"

2026-01-27 14:44:08 +00:00 · 2022-11-16 01:27:08 -08:00
parent a78caba5d4 40e4311d4b
commit b1515e3a42
29 changed files with 177 additions and 15 deletions
--- a/bindings/arm/msm/msm.txt
+++ b/bindings/arm/msm/msm.txt
@@ -108,7 +108,7 @@ SoCs:
  compatible = "qcom,anorak"

 - RAVELIN
-  compatible = "qcom,ravelin"
+  compatible = "qcom,ravelin", "qcom,ravelinp"

 - MONTAGUE
  compatible = "qcom,montague", "qcom,montaguep"
@@ -318,6 +318,9 @@ compatible = "qcom,ravelin-rumi"
 compatible = "qcom,ravelin-atp"
 compatible = "qcom,ravelin-idp"
 compatible = "qcom,ravelin-qrd"
+compatible = "qcom,ravelinp-atp"
+compatible = "qcom,ravelinp-idp"
+compatible = "qcom,ravelinp-qrd"
 compatible = "qcom,montague-rumi"
 compatible = "qcom,montague-idp"
 compatible = "qcom,montague-qrd"
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -502,13 +502,13 @@ dtbo-$(CONFIG_ARCH_RAVELIN) += ravelin-rumi-overlay.dtbo \
 	montague-rcm-overlay.dtbo

 ravelin-rumi-overlay.dtbo-base := ravelin.dtb
-ravelin-atp-overlay.dtbo-base := ravelin.dtb
-ravelin-idp-overlay.dtbo-base := ravelin.dtb
-ravelin-idp-wcn3988-overlay.dtbo-base := ravelin.dtb
-ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo-base := ravelin.dtb
-ravelin-qrd-overlay.dtbo-base := ravelin.dtb
-ravelin-idp-4gb-overlay.dtbo-base := ravelin-4gb.dtb
-ravelin-qrd-4gb-overlay.dtbo-base := ravelin-4gb.dtb
+ravelin-atp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb
+ravelin-idp-overlay.dtbo-base := ravelin.dtb ravelinp.dtb
+ravelin-idp-wcn3988-overlay.dtbo-base := ravelin.dtb ravelinp.dtb
+ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo-base := ravelin.dtb ravelinp.dtb
+ravelin-qrd-overlay.dtbo-base := ravelin.dtb ravelinp.dtb
+ravelin-idp-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb
+ravelin-qrd-4gb-overlay.dtbo-base := ravelin-4gb.dtb ravelinp-4gb.dtb
 montague-rumi-overlay.dtbo-base := montague.dtb montaguep.dtb
 montague-qrd-overlay.dtbo-base := montague.dtb montaguep.dtb
 montague-hsp-overlay.dtbo-base := montague.dtb montaguep.dtb
@@ -523,6 +523,13 @@ dtb-$(CONFIG_ARCH_RAVELIN) += ravelin-rumi.dtb \
 	ravelin-qrd.dtb \
 	ravelin-idp-4gb.dtb \
 	ravelin-qrd-4gb.dtb \
+	ravelinp-atp.dtb \
+	ravelinp-idp.dtb \
+	ravelinp-idp-wcn3988.dtb \
+	ravelinp-idp-wcn3950-amoled-rcm.dtb \
+	ravelinp-qrd.dtb \
+	ravelinp-idp-4gb.dtb \
+	ravelinp-qrd-4gb.dtb \
 	montague-rumi.dtb \
 	montague-qrd.dtb \
 	montague-hsp.dtb \
--- a/qcom/ravelin-4gb.dtsi
+++ b/qcom/ravelin-4gb.dtsi
@@ -1,4 +1,5 @@
 #include "ravelin.dtsi"
+#include "ravelin-low-memory.dtsi"
 / {
 };

--- a/qcom/ravelin-atp-overlay.dts
+++ b/qcom/ravelin-atp-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin ATP";
 	compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <33 0>;
 };
--- a/qcom/ravelin-idp-4gb-overlay.dts
+++ b/qcom/ravelin-idp-4gb-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR";
 	compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <34 0x600>;
 };
--- a/qcom/ravelin-idp-overlay.dts
+++ b/qcom/ravelin-idp-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin IDP";
 	compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <34 0>;
 };
--- a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts
+++ b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM";
 	compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <34 2>;
 };
--- a/qcom/ravelin-idp-wcn3988-overlay.dts
+++ b/qcom/ravelin-idp-wcn3988-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin IDP + WCN3988";
 	compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <34 1>;
 };
--- a/qcom/ravelin-low-memory.dtsi
+++ b/qcom/ravelin-low-memory.dtsi
@@ -0,0 +1,37 @@
+&trust_ui_vm_mem {
+	status = "disabled";
+};
+
+&trust_ui_vm_qrtr {
+	status = "disabled";
+};
+
+&trust_ui_vm_vblk0_ring {
+	status = "disabled";
+};
+
+&trust_ui_vm_swiotlb {
+	status = "disabled";
+};
+
+&non_secure_display_dma_buf {
+	status = "disabled";
+};
+
+&non_secure_display_memory {
+	status = "disabled";
+};
+
+&soc {
+	qcom,guestvm_loader@e0b00000 {
+		status = "disabled";
+	};
+
+	qrtr-gunyah {
+		status = "disabled";
+	};
+
+	qcom,virtio_backend@0 {
+		status = "disabled";
+	};
+};
--- a/qcom/ravelin-qrd-4gb-overlay.dts
+++ b/qcom/ravelin-qrd-4gb-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR";
 	compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <0x1000B 0x600>;
 };
--- a/qcom/ravelin-qrd-overlay.dts
+++ b/qcom/ravelin-qrd-overlay.dts
@@ -6,7 +6,7 @@
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin QRD";
 	compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
-	qcom,msm-id = <568 0x10000>;
+	qcom,msm-id = <568 0x10000>, <602 0x10000>;
 	qcom,board-id = <0x1000B 0>;
 };

--- a/qcom/ravelinp-4gb.dts
+++ b/qcom/ravelinp-4gb.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "ravelinp-4gb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP 4Gb SoC";
+	compatible = "qcom,ravelinp";
+	qcom,board-id = <0 0x600>;
+};
--- a/qcom/ravelinp-4gb.dtsi
+++ b/qcom/ravelinp-4gb.dtsi
@@ -0,0 +1,7 @@
+#include "ravelinp.dtsi"
+#include "ravelin-low-memory.dtsi"
+/ {
+};
+
+&soc {
+};
--- a/qcom/ravelinp-atp.dts
+++ b/qcom/ravelinp-atp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+#include "ravelinp-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP ATP";
+	compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp";
+	qcom,board-id = <33 0>;
+};
--- a/qcom/ravelinp-atp.dtsi
+++ b/qcom/ravelinp-atp.dtsi
@@ -0,0 +1 @@
+#include "ravelin-atp.dtsi"
--- a/qcom/ravelinp-idp-4gb.dts
+++ b/qcom/ravelinp-idp-4gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp-4gb.dtsi"
+#include "ravelinp-idp-4gb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP IDP 4GB DDR";
+	compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
+	qcom,board-id = <0x34 0x600>;
+};
--- a/qcom/ravelinp-idp-4gb.dtsi
+++ b/qcom/ravelinp-idp-4gb.dtsi
@@ -0,0 +1 @@
+#include "ravelin-idp.dtsi"
--- a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts
+++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+#include "ravelinp-idp-wcn3950-amoled-rcm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP WCN3950 IDP + AMOLED + RCM";
+	compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
+	qcom,board-id = <34 2>;
+};
--- a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi
+++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi
@@ -0,0 +1 @@
+#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"
--- a/qcom/ravelinp-idp-wcn3988.dts
+++ b/qcom/ravelinp-idp-wcn3988.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+#include "ravelinp-idp-wcn3988.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP IDP + WCN3988";
+	compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
+	qcom,board-id = <34 1>;
+};
--- a/qcom/ravelinp-idp-wcn3988.dtsi
+++ b/qcom/ravelinp-idp-wcn3988.dtsi
@@ -0,0 +1 @@
+#include "ravelin-idp-wcn3988.dtsi"
--- a/qcom/ravelinp-idp.dts
+++ b/qcom/ravelinp-idp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+#include "ravelinp-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP IDP";
+	compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp";
+	qcom,board-id = <34 0>;
+};
--- a/qcom/ravelinp-idp.dtsi
+++ b/qcom/ravelinp-idp.dtsi
@@ -0,0 +1 @@
+#include "ravelin-idp.dtsi"
--- a/qcom/ravelinp-qrd-4gb.dts
+++ b/qcom/ravelinp-qrd-4gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp-4gb.dtsi"
+#include "ravelinp-qrd-4gb.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP QRD 4GB DDR";
+	compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd";
+	qcom,board-id = <0x1000B 0x600>;
+};
--- a/qcom/ravelinp-qrd-4gb.dtsi
+++ b/qcom/ravelinp-qrd-4gb.dtsi
@@ -0,0 +1 @@
+#include "ravelin-qrd.dtsi"
--- a/qcom/ravelinp-qrd.dts
+++ b/qcom/ravelinp-qrd.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+#include "ravelinp-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP QRD";
+	compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};
+
--- a/qcom/ravelinp-qrd.dtsi
+++ b/qcom/ravelinp-qrd.dtsi
@@ -0,0 +1 @@
+#include "ravelin-qrd.dtsi"
--- a/qcom/ravelinp.dts
+++ b/qcom/ravelinp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "ravelinp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP SoC";
+	compatible = "qcom,ravelinp";
+	qcom,board-id = <0 0>;
+};
+
--- a/qcom/ravelinp.dtsi
+++ b/qcom/ravelinp.dtsi
@@ -0,0 +1,10 @@
+#include "ravelin.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. RavelinP";
+	compatible = "qcom,ravelinp";
+	qcom,msm-id = <602 0x10000>;
+};
+
+&ipa_hw {
+	status = "disabled";
+};
				`@@ -0,0 +1 @@`
				`#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"`