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ARM: dts: qcom: adding low lat data pipe feature availability

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Adding DTSI changes to enable low lat data pipe and to get the
values of GSI MSI address, GSI MSI clear address and interrupt
vectors for QMAP flow control and low lat pipe.

Change-Id: Ie4beefc8b2fb8140798182975d1f380270d4594a
This commit is contained in:
Michael Adisumarta
2021-04-23 17:12:50 -07:00
parent 5001b4a0ab
commit b1c2d7b248
2 changed files with 19 additions and 2 deletions
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10
bindings/platform/msm/ipa.txt
View File

@@ -21,6 +21,8 @@ IPA node:
- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
"bam-irq" - string to identify the IPA BAM interrupt.
"a2-bam-irq" - string to identify the A2 BAM interrupt.
"msi-irq-rmnet-ctl" - string to identify QMAP MSI interrupt
"msi-irq-rmnet-ll" - string to identify LL MSI interrupt
- qcom,ipa-hw-ver: Specifies the IPA hardware version.
- qcom,ipa-ram-mmap: An array of unsigned integers representing addresses and
sizes which are used by the driver to access IPA RAM.
@@ -128,6 +130,14 @@ memory allocation over a PCIe bridge
2 (override scm call as though it returned false)
- qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event
rings read pointer should be read from the ddr.
- qcom,rmnet-ll-enable: Flag to indicate low latency data channels should be supported
for the target
- qcom,gsi-msi-addr: APSS_GICA_SETSPI_NSR register address for IPA firmware to write
the MSI IRQ number to get the ISR triggered
- qcom,gsi-msi-clear-addr: APSS_GICA_CLRSPI_NSR register address for IPA driver to write
the MSI IRQ number to clear the respective interrupt
- qcom,gsi-rmnet-ctl-evt-ring-intvec: Integer vector value for the QMAP flow control pipe
- qcom,gsi-rmnet-ll-evt-ring-intvec: Integer vector value for the low lat data pipe
IPA pipe sub nodes (A2 static pipes configurations):

11
qcom/waipio.dtsi
View File

@@ -3343,8 +3343,10 @@
qcom,ipa-cfg-offset = <0x0140000>;
interrupts =
<0 654 IRQ_TYPE_LEVEL_HIGH>,
<0 432 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
<0 432 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq", "msi-irq-rmnet-ctl", "msi-irq-rmnet-ll";
qcom,ipa-hw-ver = <22>; /* IPA core version = IPAv5.1 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <1>; /* MSM platform */
@@ -3362,6 +3364,11 @@
qcom,tx-poll;
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,rmnet-ll-enable;
qcom,gsi-msi-addr = <0x17110040>;
qcom,gsi-msi-clear-addr = <0x17110048>;
qcom,gsi-rmnet-ctl-evt-ring-intvec = <521>;
qcom,gsi-rmnet-ll-evt-ring-intvec = <522>;
qcom,ipa-uc-holb-monitor;
qcom,ipa-holb-monitor-poll-period = <5>;
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;