Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees synced 2026-02-01 08:51:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge "ARM: dts: msm: Add pipe_div2_clk for PCIe1 and PCIe2 of anorak"

Browse Source
This commit is contained in:
qctecmdr
2022-09-01 21:03:22 -07:00
committed by Gerrit - the friendly Code Review server
parent e07102c2b5 7a4c3f5b7a
commit b3feb5c4a4
1 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
qcom/anorak-pcie.dtsi
View File

@@ -87,6 +87,7 @@
<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_QMIP_PCIE_AHB_CLK>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
@@ -97,11 +98,12 @@
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk",
"pcie_aggre_noc_sf_axi_clk",
"pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_pipe_clk_mux",
"pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk",
"gcc_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>,
<0>, <0>, <0>, <0>, <0>, <0>, <0>;
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
@@ -354,6 +356,7 @@
<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
<&pcie_1_pipe_clk>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
@@ -362,11 +365,11 @@
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk", "pcie_aggre_noc_sf_axi_clk",
"pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
"pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_pipe_clk_mux",
"pcie_1_pipe_div2_clk", "pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>, <0>;
<0>, <0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_PHY_BCR>;