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bindings: pinctrl: Add device-tree bindings for Cape pinctrl driver
Add documentation describing the device-tree properties for the Cape pinctrl driver. Change-Id: I326ce32c7f20d58206c21632a18ad8074a958f5c
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Auditya Bhattaram
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bindings/pinctrl/qcom,cape-pinctrl.yaml
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182
bindings/pinctrl/qcom,cape-pinctrl.yaml
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,cape-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. CAPE TLMM block
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description: |
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This binding describes the Top Level Mode Multiplexer block found in the
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CAPE platform.
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properties:
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compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,cape-pinctrl"
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reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the TLMM register space.
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interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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#interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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#gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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wakeup-parent:
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Usage: optional
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Value type: <phandle>
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Definition: A phandle to the wakeup interrupt controller for the SoC.
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode.
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Valid pins:
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gpio0-gpio169
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Supports mux, bias and drive-strength
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sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
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Supports bias and drive-strength
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function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values:
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gpio, atest_char, atest_char0, atest_char1, atest_char2,
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atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
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atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
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dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
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jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
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mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
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mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
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mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
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phase_flag0, phase_flag1, phase_flag10, phase_flag11,
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phase_flag12, phase_flag13, phase_flag14, phase_flag15,
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phase_flag16, phase_flag17, phase_flag18, phase_flag19,
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phase_flag2, phase_flag20, phase_flag21, phase_flag22,
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phase_flag23, phase_flag24, phase_flag25, phase_flag26,
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phase_flag27, phase_flag28, phase_flag29, phase_flag3,
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phase_flag30, phase_flag31, phase_flag4, phase_flag5,
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phase_flag6, phase_flag7, phase_flag8, phase_flag9,
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pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
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prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
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qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
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qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
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qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
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qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
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qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
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qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
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qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
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qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
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tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
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tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
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uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
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uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
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vsense_trigger
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bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull up.
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output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven high.
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Not valid for sdc pins.
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output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven low.
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Not valid for sdc pins.
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drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
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examples:
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- |
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tlmm: pinctrl@f000000 {
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compatible = "qcom,cape-pinctrl";
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reg = <0x0F000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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