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ARM: dts: msm: Update QMP Phy init sequence for Lahaina

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Update the QMP phy init sequence as per the HSR v1.08 and HSR v0.94
update for DP Combo phy and Uni Phy respectively.

Change-Id: I0fd5bd28abe2db64106bf17ff6480ef13f77612e
This commit is contained in:
Elson Roy Serrao
2020-04-09 11:55:01 -07:00
parent f99558c8ed
commit ba6ab37ffa
1 changed files with 6 additions and 6 deletions
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12
qcom/lahaina-usb.dtsi
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@@ -312,7 +312,7 @@
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
USB3_DP_PCS_CDR_RESET_TIME 0x0F 0
USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
@@ -492,11 +492,11 @@
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7F 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0xBD 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5C 0
@@ -535,7 +535,7 @@
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xA9 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0