mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Add dsp device nodes for Anorak
Update adsp and cdsp device nodes for Anorak. Change-Id: I172eac1315f48be0ca8beb33d0700361cf8d5492
This commit is contained in:
sandheep
@@ -4,5 +4,16 @@
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qcom,dma-heaps {
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compatible = "qcom,dma-heaps";
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qcom,secure_cdsp {
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qcom,dma-heap-name = "qcom,cma-secure-cdsp";
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qcom,dma-heap-type = <HEAP_TYPE_CMA>;
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memory-region = <&cdsp_secure_heap_mem>;
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};
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qcom,adsp {
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qcom,dma-heap-name = "qcom,adsp";
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qcom,dma-heap-type = <HEAP_TYPE_CMA>;
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memory-region = <&adsp_mem>;
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};
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};
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};
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203
qcom/anorak.dtsi
203
qcom/anorak.dtsi
@@ -175,6 +175,15 @@
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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adsp_mem_heap: adsp_heap_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xC00000>;
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};
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};
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&firmware {
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@@ -601,6 +610,12 @@
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0x2000 3
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0x4400 2>;
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};
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qcom,msm_fastrpc_rpmsg {
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compatible = "qcom,msm-fastrpc-rpmsg";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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};
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};
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};
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@@ -658,6 +673,12 @@
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0x2000 3
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0x4400 2>;
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};
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qcom,msm_fastrpc_rpmsg {
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compatible = "qcom,msm-fastrpc-rpmsg";
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qcom,glink-channels = "fastrpcglink-apps-dsp";
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qcom,intents = <0x64 64>;
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};
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};
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};
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@@ -838,6 +859,188 @@
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qcom,vmid-cp-camera-preview-ro;
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};
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qcom,msm-cdsp-loader {
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compatible = "qcom,cdsp-loader";
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qcom,proc-img-to-load = "cdsp";
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qcom,rproc-handle = <&cdsp_pas>;
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};
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qcom,msm-adsprpc-mem {
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compatible = "qcom,msm-adsprpc-mem-region";
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memory-region = <&adsp_mem_heap>;
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restrict-access;
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};
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msm_fastrpc: qcom,msm_fastrpc {
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compatible = "qcom,msm-fastrpc-compute";
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qcom,adsp-remoteheap-vmid = <22 37>;
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qcom,fastrpc-adsp-audio-pdr;
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qcom,fastrpc-adsp-sensors-pdr;
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qcom,rpc-latency-us = <235>;
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qcom,fastrpc-gids = <2908>;
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qcom,qos-cores = <2>; /* its a gold+ cluster */
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qcom,msm_fastrpc_compute_cb1 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0961 0x0420>,
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<&apps_smmu 0x2021 0x0560>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb2 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0962 0x0400>,
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<&apps_smmu 0x2022 0x0460>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb3 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0963 0x0C60>,
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<&apps_smmu 0x2023 0x0420>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb4 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0964 0x0560>,
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<&apps_smmu 0x2024 0x2420>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb5 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0965 0x0540>,
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<&apps_smmu 0x2025 0x0520>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb6 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0966 0x0440>,
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<&apps_smmu 0x2026 0x2520>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb7 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0967 0x0520>,
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<&apps_smmu 0x2027 0x0560>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb8 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x0968 0x0440>,
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<&apps_smmu 0x2028 0x0420>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb9 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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qcom,secure-context-bank;
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iommus = <&apps_smmu 0x0969 0x0560>,
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<&apps_smmu 0x2029 0x2520>;
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qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb10 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "adsprpc-smd";
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iommus = <&apps_smmu 0x2803 0x0>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb11 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "adsprpc-smd";
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iommus = <&apps_smmu 0x2804 0x0>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb12 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "adsprpc-smd";
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iommus = <&apps_smmu 0x2805 0x0>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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shared-cb = <5>;
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};
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qcom,msm_fastrpc_compute_cb13 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x096B 0x0400>,
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<&apps_smmu 0x202B 0x2420>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb14 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x096C 0x0C60>,
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<&apps_smmu 0x202C 0x0460>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb15 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x096D 0x0D00>,
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<&apps_smmu 0x202D 0x2420>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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qcom,msm_fastrpc_compute_cb16 {
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compatible = "qcom,msm-fastrpc-compute-cb";
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label = "cdsprpc-smd";
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iommus = <&apps_smmu 0x096E 0x0560>,
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<&apps_smmu 0x202E 0x0460>;
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qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
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qcom,iommu-faults = "stall-disable", "HUPCF";
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dma-coherent;
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};
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};
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qcom,mem-buf-msgq {
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compatible = "qcom,mem-buf-msgq";
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};
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