mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
dt-bindings: Adding pinctrl devicetree documentation for Anorak
Adding pinctrl devicetree documentation for Anorak platform Change-Id: Ifb9352218573c07906af9828fb2df2e00ed45a26
This commit is contained in:
Kamati Srinivas
186
bindings/pinctrl/qcom,anorak-pinctrl.yaml
Normal file
186
bindings/pinctrl/qcom,anorak-pinctrl.yaml
Normal file
@@ -0,0 +1,186 @@
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,anorak-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. ANORAK TLMM block
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
ANORAK platform.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,anorak-pinctrl"
|
||||
|
||||
reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
#interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
#gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
wakeup-parent:
|
||||
Usage: optional
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the wakeup interrupt controller for the SoC.
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins:
|
||||
gpio0-gpio223
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values:
|
||||
gpio, FORCED_USB, atest_char, atest_char0, atest_char1,
|
||||
atest_char2, atest_char3, atest_usb0, atest_usb00,
|
||||
atest_usb01, atest_usb02, atest_usb03, audio_ref, boot0,
|
||||
boot1, boot10, boot11, boot2, boot3, boot4, boot5, boot6,
|
||||
boot7, boot8, boot9, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer10, cci_timer11,
|
||||
cci_timer12, cci_timer13, cci_timer14, cci_timer2,
|
||||
cci_timer3, cci_timer4, cci_timer5, cci_timer6, cci_timer7,
|
||||
cci_timer8, cci_timer9, cmu_rng0, cmu_rng1, cmu_rng2,
|
||||
cmu_rng3, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
|
||||
ddr_pxi3, dp0_hot, edp0_hot, edp0_lcd, edp1_hot, edp1_lcd,
|
||||
ext_mclk0, ext_mclk1, gcc_gp1, gcc_gp10, gcc_gp11, gcc_gp2,
|
||||
gcc_gp3, gcc_gp4, gcc_gp5, gcc_gp6, gcc_gp7, gcc_gp8, gcc_gp9,
|
||||
i2s0_data0,i2s0_data1, i2s0_sck, i2s0_ws, i2s2_data0,
|
||||
i2s2_data1, i2s2_sck, i2s2_ws, ibi_i3c, jitter_bist,
|
||||
mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
|
||||
mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
|
||||
mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
|
||||
mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
|
||||
pcie0_clk, pcie1_clk, pcie2_clk, phase_flag0, phase_flag1,
|
||||
phase_flag10, phase_flag11, phase_flag12, phase_flag13,
|
||||
phase_flag14, phase_flag15, phase_flag16, phase_flag17,
|
||||
phase_flag18, phase_flag19, phase_flag2, phase_flag20,
|
||||
phase_flag21, phase_flag22, phase_flag23, phase_flag24,
|
||||
phase_flag25, phase_flag26, phase_flag27, phase_flag28,
|
||||
phase_flag29, phase_flag3, phase_flag30, phase_flag31, phase_flag4,
|
||||
phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9,
|
||||
pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3,
|
||||
pwm_0, pwm_1, pwm_2, pwm_3, pwm_4, pwm_5, pwm_6, pwm_7, pwm_8,
|
||||
pwm_9, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10,
|
||||
qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
|
||||
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
|
||||
qdss_gpio7, qdss_gpio8, qdss_gpio9, qup0_se0, qup0_se1, qup0_se2,
|
||||
qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup1_se0, qup1_se1,
|
||||
qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, sd_write,
|
||||
tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0,
|
||||
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2,
|
||||
usb0_phy, usb2phy_ac, vsense_trigger
|
||||
|
||||
bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
examples:
|
||||
- |
|
||||
tlmm: pinctrl@f000000 {
|
||||
compatible = "qcom,anorak-pinctrl";
|
||||
reg = <0xf000000 0x1000000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
}
|
||||
Reference in New Issue
Block a user