Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: Enable CPUFREQ-HW and CPUFREQ-HW-debug on RAVELIN"

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qctecmdr
2022-10-25 21:50:57 -07:00
committed by Gerrit - the friendly Code Review server
parent a72cc5c9a2 2318f6f7d4
commit c09279883f
2 changed files with 34 additions and 1 deletions
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4
qcom/ravelin-rumi.dtsi
View File

@@ -205,3 +205,7 @@
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};

31
qcom/ravelin.dtsi
View File

@@ -20,7 +20,9 @@
#address-cells = <2>;
#size-cells = <2>;
chosen: chosen { };
chosen: chosen {
bootargs = "cpufreq.default_governor=performance";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
@@ -47,6 +49,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -69,6 +72,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
@@ -86,6 +90,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
@@ -103,6 +108,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
@@ -121,6 +127,7 @@
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -136,6 +143,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
@@ -153,6 +161,7 @@
cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 2>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
@@ -170,6 +179,7 @@
cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 2>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
@@ -807,6 +817,25 @@
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;