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ARM: dts: msm: Remove qcom,dwc-usb3-msm-tx-fifo-size property

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MSM USB DWC3 driver does not depend on this property to know
the TXFIFO size in the USB controller. Remove any reference to
qcom,dwc-usb3-msm-tx-fifo-size property.

Change-Id: I321f041b44cb35033f9bcdd1b6cba0f3fb9da8b5
This commit is contained in:
Pavankumar Kondeti
2022-01-20 15:16:05 +05:30
parent 3e46428cad
commit c1f9e55bc3
10 changed files with 0 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
bindings/usb/msm-ssusb.txt
View File

@@ -51,8 +51,6 @@ Optional properties :
regulator node to the USB controller.
- dpdm-supply: phandle to dpdm supply which will be used to drive dp/dm lines
in high-z state.
- qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for
TX fifo allocation in bytes
- qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source
after USB is kept into LPM.
- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode.
@@ -117,7 +115,6 @@ Example MSM USB3.0 controller device node :
USB3_GDSC-supply = <&gdsc_usb30>;
qcom,dwc-usb3-msm-dbm-eps = <4>
qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>;
qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
qcom,usb-dbm = <&dbm_1p4>;
qcom,lpm-to-suspend-delay-ms = <2>;
qcom,num-gsi-evt-buffs = <0x2>;

1
qcom/cape-usb.dtsi
View File

@@ -44,7 +44,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,

1
qcom/diwali-usb.dtsi
View File

@@ -44,7 +44,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,

1
qcom/holi-usb.dtsi
View File

@@ -54,7 +54,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
dwc3@4e00000 {
compatible = "snps,dwc3";

2
qcom/lahaina-usb.dtsi
View File

@@ -47,7 +47,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
usb-role-switch;
extcon = <&eud>;
@@ -383,7 +382,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,

2
qcom/neo-usb.dtsi
View File

@@ -29,8 +29,6 @@
qcom,core-clk-rate = <133333333>;
qcom,core-clk-rate-hs = <66666667>;
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xe000>;

2
qcom/parrot-usb.dtsi
View File

@@ -29,8 +29,6 @@
qcom,core-clk-rate = <133333333>;
qcom,core-clk-rate-hs = <66666667>;
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd800>;

1
qcom/sdxlemur-usb.dtsi
View File

@@ -38,7 +38,6 @@
0x240 /* GSI_RING_BASE_ADDR_L */
0x25c /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
dwc3@a600000 {
compatible = "snps,dwc3";

1
qcom/shima-usb.dtsi
View File

@@ -46,7 +46,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
usb-role-switch;
extcon = <&eud>;

1
qcom/waipio-usb.dtsi
View File

@@ -44,7 +44,6 @@
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,