Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add interconnect devices for RAVELIN

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Add interconnect devices for clk_virt_noc, mc_virt_noc, aggre1_noc,
aggre2_noc, cnoc2_noc, cnoc3_noc, gem_noc, lpass_ag_noc, mmss_noc,
pcie_anoc, system_noc and video_aggre_noc. This will allow
consumers to get their path and set bandwidth constraints on them.

Change-Id: I5115bc9ef412bb720c434f2857df8cfc1abcdabc
This commit is contained in:
Raviteja Laggyshetty
2022-09-07 19:21:57 +05:30
parent 92192ecd86
commit c7e8afa85b
1 changed files with 100 additions and 0 deletions
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100
qcom/ravelin.dtsi
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@@ -7,6 +7,8 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,ravelin.h>
/ {
model = "Qualcomm Technologies, Inc. Ravelin";
@@ -284,6 +286,10 @@
<WAKE_TCS 3>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
};
disp_rsc: rsc@af20000 {
@@ -838,6 +844,100 @@
memory-region = <&adsp_mem_heap>;
restrict-access;
};
clk_virt: interconnect@0 {
compatible = "qcom,ravelin-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1 {
compatible = "qcom,ravelin-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
reg = <0x16E0000 0x13080>;
compatible = "qcom,ravelin-aggre1_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x1700000 0x1B080>;
compatible = "qcom,ravelin-aggre2_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
cnoc2: interconnect@1500000 {
reg = <0x1500000 0x6200>;
compatible = "qcom,ravelin-cnoc2";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
conc3: interconnect@1510000 {
reg = <0x01510000 0xF200>;
compatible = "qcom,ravelin-cnoc3";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@19100000 {
reg = <0x19100000 0xBC080>;
compatible = "qcom,ravelin-gem_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3C40000 {
reg = <0x3C40000 0x17200>;
compatible = "qcom,ravelin-lpass_ag_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
reg = <0x1740000 0x19080>;
compatible = "qcom,ravelin-mmss_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie_anoc: interconnect@16C0000 {
reg = <0x16C0000 0x7080>;
compatible = "qcom,ravelin-pcie_anoc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
reg = <0x1680000 0x19080>;
compatible = "qcom,ravelin-system_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
video_aggre_noc: interconnect@1760000 {
reg = <0x1760000 0x1100>;
compatible = "qcom,ravelin-video_aggre_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
};
#include "ravelin-pinctrl.dtsi"