mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Add higher corners and ACD configurations for anorak gpu
Anorak GPU supports additional higher gpu power levels. Also, add ACD control register configurations that contain the DVM values for ACD throttling. Change-Id: I2574c60e7ebd5aa4a5ecee9b25eb767a085df45f
This commit is contained in:
@@ -34,7 +34,7 @@
|
||||
|
||||
qcom,chipid = <0x43050b00>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
qcom,no-nap;
|
||||
|
||||
@@ -79,62 +79,110 @@
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <681000000>;
|
||||
qcom,gpu-freq = <788000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <750000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <730000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <690000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <640000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <599000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <492000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xc0295ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <285000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0xe02a5ffd>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -241,5 +289,8 @@
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
};
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user